Managing power consumption in a multi-core processor

A processor comprising:

• an uncore area, wherein the uncore area comprises a power management unit and a second voltage regulator, wherein the second voltage regulator is to provide a second regulated voltage (VR) to the uncore area, via a second supply pin of the uncore area coupled to a second load resistor, and
• a core area, wherein the core area includes a plurality of functional blocks, a plurality of sensors, an activity accumulation logic, a throttling logic, a throttler, and a first voltage regulator, wherein the first voltage regulator is to provide a first VR to the core area independently of the second VR, via a first supply pin of the core area coupled to a first load resistor, wherein the power management unit is to detect an event based on which the core area is to enter a deep power saving state in which the first VR is to be substantially cut off and in response provide a first voltage value to the second voltage regulator to cause the second voltage regulator to decrease the second VR from a normal reference voltage value to a reduced reference voltage value based on the first voltage value to cause a reduction in a pin voltage value provided at the second supply pin of the uncore area, wherein the reduction in the pin voltage value is to decrease a power consumed by the uncore area, the pin voltage value to be decreased to a level sufficient to maintain a minimum pin voltage value to operate the processor at a specified frequency value.