US 9,069,548 B2 · Reconfigurable instruction encoding method and processor architecture

Abstract

A reconfigurable instruction encoding method includes the following operations: An instruction distribution of an application is counted, and multiple instruction pairs with higher utilization rates are accordingly found. Multiple instructions of the instruction pairs are duplicately encoded according to multiple reserved sections of an original instruction table, so that the instructions have corresponding reconfigured codes and a reconfigured instruction table extended from the original instruction table and including the reconfigured codes is obtained. A compiler is utilized to generate multiple machine codes according to the reconfigured instruction table and consecutive execution instructions. Hamming distance of the machine codes corresponding to the reconfigured instruction table and the execution instructions are not longer than Hamming distance of the machine codes generated according to the original instruction table and the execution instructions.

Claims10

Dependent claims

A reconfigurable instruction encoding method, applied to an instruction encoding system, comprising:

counting an instruction distribution of an application, and accordingly finding a plurality of instruction pairs with higher utilization rates;
and
repeatedly encoding a plurality of instructions of the instruction pairs according to a plurality of reserved sections of an original instruction table, so that each of the instructions has an original code and a reconfigured code and a reconfigured instruction table extended from the original instruction table and including the reconfigured codes is obtained;
and
generating a plurality of machine codes according to the reconfigured instruction table and a plurality of consecutive execution instructions;
wherein a Hamming distance of the machine codes generated according to the reconfigured instruction table and the execution instructions are not longer than that generated according to the original instruction table and the execution instructions.

3 more elements

A processor, comprising:

an instruction fetch unit for obtaining a plurality of machine codes corresponding to a plurality of consecutive execution instructions of an application;
an instruction re-encoding unit for loading a reconfigured instruction table, determining whether the machine codes are a plurality of reconfigured codes according to the reconfigured instruction table, and transforming the reconfigured codes into a plurality of original codes corresponding to the execution instructions when the machine codes are the reconfigured codes;
a multiplexer, coupled to the instruction fetch unit and the instruction re-encoding unit, for outputting the original codes when the machine codes are the reconfigured codes;
an instruction decoding unit for decoding the original codes to be the corresponding execution instructions;
and
an execution unit for executing the execution instructions;
wherein the reconfigured instruction table includes an original instruction table and the reconfigured codes, and the reconfigured codes are obtained by repeatedly encoding a plurality of instructions of a plurality of instruction pairs, with higher utilization rates in the application, according to a plurality of reserved sections of the original instruction table.

4 more elements

Dependencies are inferred from the claim text.

Reconfigurable instruction encoding method and processor architecture

Life of this patent

Reconfigurable instruction encoding method and processor architecture

Life of this patent

Abstract

Claims10