Instruction and logic for processing text strings
AssigneeIntel Corporation
InventorsMichael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
Life of this patent
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Abstract
Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
Claims30
A tangible non-transitory computer-readable medium to record functional descriptive material including executable instructions, said computer-readable medium having recorded thereon a single SIMD (Single Instruction, Multiple Data) instruction, which if executed by a computer causes the computer to
- compare each data element of a first packed operand with each data element of a second packed operand;
- and
- store a first result of the comparison.
An apparatus comprising:
- a processor comparison logic circuit to compare only valid data elements of a first operand to only valid data elements of a second operand in response to a single SIMD instruction;
- a first control signal to control the comparison logic.
An apparatus comprising:
- a processor comparison logic circuit to compare only valid data elements of a first operand to only valid data elements of a second operand in response to a single SIMD instruction;
- a first control signal to control the comparison logic, wherein the first control signal includes a sign control signal to indicate whether the comparison logic is to compare signed or unsigned values and an aggregation function signal to indicate whether the comparison logic is to perform an aggregation function chosen from a list consisting of:
- any equal, equal range, each equal, non-contiguous sub-strings, and equal order.
A system comprising
- a first memory to store a SIMD comparison instruction;
- a processor to perform the SIMD comparison instruction to compare at least any valid data elements of a first operand to each of any valid data elements of a second operand indicated by the SIMD comparison instruction.
A system comprising
- a first memory to store a SIMD comparison instruction;
- a processor to perform the SIMD comparison instruction to compare at least any valid data elements of a first operand to each of any valid data elements of a second operand indicated by the SIMD comparison instruction, wherein the instruction is to cause only explicitly valid data elements of the first and second operands to be compared.
A processor comprising:
- a first storage area to store a first packed operand corresponding to a first text string;
- a second storage area to store a second packed operand corresponding to a second text string;
- a comparison logic circuit to compare all valid data elements of the first packed operand with all valid data elements of the second packed operand in response to a single SIMD instruction;
- a third storage area to store a result array of the comparison performed by the comparison logic.
Dependencies are inferred from the claim text.