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US 9,069,489 B1Granted
Dynamic random access memory front end
AssigneeMarvell Israel (M.I.S.L) Ltd.
InventorNoam Mizrahi
Life of this patent
Estimating the term…
Abstract
Some of the embodiments of the present disclosure provide a method comprising receiving a first set of memory access commands; modifying the first set of memory access commands to generate a second set of memory access commands; and in response to said generation of the second set of memory access commands, issuing the second set of memory access commands to a memory. Other embodiments are also described and claimed.
Claims14
An apparatus for accessing a memory, the apparatus comprising:
- a buffer comprising (i) a first buffer bank configured to receive and store a first plurality of memory access commands for accessing a first memory bank of the memory and (ii) a second buffer bank configured to receive and store a second plurality of memory access commands for accessing a second memory bank of the memory;
- a first level of arbiters configured to control an order in which memory access commands are output by individual buffer banks, the first level of arbiters comprising (i) a first arbiter configured to control an order in which the first plurality of memory access commands are output by the first buffer bank and (ii) a second arbiter configured to control an order in which the second plurality of memory access commands are output by the second buffer bank, wherein the first buffer bank is configured to receive and store the first plurality of memory access commands in a first order, wherein the first buffer bank is configured to output the first plurality of memory access commands in a second order that is different from the first order, wherein the second buffer bank is configured to receive and store the second plurality of memory access commands in a third order, and wherein the second buffer bank is configured to output the second plurality of memory access commands in a fourth order that is different from the third order;
- and
- a second level of arbiter configured to control an order in which the memory access commands are output from the first and second buffer banks to the memory.
1 more element
A method comprising:
- receiving, (i) at a first buffer bank of a buffer and in a first order, a first plurality of memory access commands for accessing a first memory bank of a memory, and (ii) at a second buffer bank of the buffer and in a second order, a second plurality of memory access commands for accessing a second memory bank of the memory;
- controlling, by a first level of arbiters, an order in which memory access commands are output respectively by individual buffer banks, the first level of arbiters comprising a first arbiter and a second arbiter, wherein controlling the order in which memory access commands are output by individual buffer banks comprises:
- (i) controlling, by the first arbiter, an order in which the first plurality of memory access commands are output by the first buffer bank such that the first plurality of memory access commands are output by the first buffer bank in a third order that is different from the first order and (ii) controlling, by the second arbiter, an order in which the second plurality of memory access commands are output by the second buffer bank such that the second plurality of memory access commands are output by the second buffer bank in a fourth order that is different from the second order;
- and
- controlling, by a second level of arbiter, an order in which the memory access commands are output from the first and second buffer banks to the memory.
2 more elements
Dependencies are inferred from the claim text.