Timing controller and liquid crystal display comprising the timing controller

#This application is a Section 371 of International Application No. PCT/CN2011/078490, filed Aug. 16, 2011, which has not yet been published by the International Bureau, and the disclosure of which is incorporated herein by reference.

#The present invention relates to the field of liquid crystal display, in particular, to a timing controller and a liquid crystal display comprising the timing controller.

#The timing controller (TCON) is a chip in the liquid crystal display (LCD) module, and is used to receive video stream data from a video signal processing device (such as a multimedia processor or an image processor), conduct serial processing on the video stream data and form a drive signal which drives multiple source driver integrated circuits, so that the source driver integrated circuits form different data voltages to drive the display flat panel to display different images.

#The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.

#In the drawings:

#FIG. 1 is a schematic view of the structure of the liquid crystal display screen in the prior art;

#The embodiments of the present invention will be detailed hereinafter in conjunction with the accompanying drawings. However, the present invention can be implemented via multiple embodiments defined and covered by the claims.

#FIG. 3 is a schematic view of the principle of the timing controller according to embodiment 1 of the present invention. As shown in FIG. 3, the timing controller comprises a data converting module 10, a memory 30 and an output module 50.

#Wherein, the data converting module 10 is used to convert inputted serial video stream data into parallel video stream data; the memory 30 connected with the data converting module 10 is used to store the parallel video stream data; the output module 50 connected with the memory 30 is used to generate a predetermined clock signal and output the parallel video stream data under the control of the predetermined clock signal.