Self aligned patterning with multiple resist layers
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Feng Shieh, Ken-Hsien Hsieh, Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu
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Abstract
A method for using self aligned multiple patterning with multiple resist layers includes forming a first patterned resist layer onto a substrate, forming a spacer layer on top of the first patterned resist layer such that spacer forms on side walls of features of the first resist layer, and forming a second patterned resist layer over the spacer layer and depositing a masking layer. The method further includes performing a planarizing process to expose the first patterned resist layer, removing the first resist layer, removing the second resist layer, and exposing the substrate.
Claims18
A method for fabricating an integrated circuit, the method comprising:
- forming a first patterned resist layer onto a substrate;
- forming a spacer layer over the first patterned resist layer such that spacer forms on side walls of features of the first patterned resist layer;
- forming a second patterned resist layer over the spacer layer and depositing a masking layer;
- removing a portion of the second patterned resist layer to expose the first patterned resist layer;
- removing the remaining first and second resist layers;
- and
- exposing the substrate.
A method for forming a fabricated circuit, the method comprising:
- forming a first patterned resist layer onto a substrate;
- forming a spacer layer on top of the first patterned resist layer such that spacer forms on side walls of features of the first resist layer;
- forming a second patterned resist layer over the spacer layer;
- depositing a masking layer on the second resist layer;
- performing a planarizing process to expose the first patterned resist layer;
- and
- removing the first patterned resist layer and the second patterned resist layer to expose a portion of the substrate.
A method for forming a fabricated circuit, the method comprising:
- forming a first patterned resist layer onto a substrate;
- forming a spacer layer on top of the first patterned resist layer such that spacer forms on side walls of features of the first resist layer;
- depositing a masking layer on the spacer layer;
- forming a second patterned resist layer on the masking layer;
- etching away regions of the masking layer not covered by the second patterned resist layer;
- removing the second patterned resist layer;
- performing a planarizing process to expose the first patterned resist layer;
- and
- removing the first patterned resist layer to expose a portion of the substrate.
Dependencies are inferred from the claim text.