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US 9,069,043 B2Granted
Termination circuit, semiconductor device, and test system
AssigneeFujitsu Limited
InventorsToshihide Suzuki, Yoichi Kawano
Life of this patent
Estimating the term…
Abstract
A termination circuit includes a pMOS transistor configured to have a source connected with a signal terminal outputting or inputting a transmission signal, a drain connected with a grounding line, and a gate receiving a control signal, the pMOS transistor being turned on when enabling a characteristic impedance matching function and being turned off when disabling the matching function; and an inductor and a capacitor configured to be connected with the signal terminal for matching characteristic impedance.
Claims8
A termination circuit comprising:
- a pMOS transistor configured to have a source connected with a signal terminal outputting or inputting a transmission signal, a drain connected with a grounding line, and a gate receiving a control signal, the pMOS transistor being turned on when enabling a characteristic impedance matching function and being turned off when disabling the matching function;
- and
- an inductor and a capacitor configured to be connected with the signal terminal for matching characteristic impedance,
- wherein a back gate of the pMOS transistor receives a voltage higher than a voltage obtained by subtracting a forward direction voltage to make a p-n junction of the pMOS transistor turn on, from a maximum voltage of the transmission signal.
1 more element
A semiconductor device comprising:
- a termination circuit including
- a pMOS transistor configured to have a source connected with a signal terminal outputting or inputting a transmission signal, a drain connected with a grounding line, and a gate receiving a control signal, the pMOS transistor being turned on when enabling a characteristic impedance matching function and being turned off when disabling the matching function, and
- an inductor and a capacitor configured to be connected with the signal terminal for matching characteristic impedance;
- a generating circuit configured to be connected with the signal terminal of the termination circuit for generating the transmission signal output from the signal terminal;
- a control terminal configured to receive the control signal;
- and
- a power detection circuit configured to be connected with the signal terminal for monitoring electric power of the transmission signal to output a signal value indicating a value of the monitored electric power.
4 more elements
A semiconductor device comprising:
- a termination circuit including
- a pMOS transistor configured to have a source connected with a signal terminal outputting or inputting a transmission signal, a drain connected with a grounding line, and a gate receiving a control signal, the pMOS transistor being turned on when enabling a characteristic impedance matching function and being turned off when disabling the matching function, and
- an inductor and a capacitor configured to be connected with the signal terminal for matching characteristic impedance;
- a processing circuit configured to be connected with the signal terminal of the termination circuit for processing the transmission signal input to the signal terminal;
- a control terminal configured to receive the control signal;
- a test terminal configured to receive a test signal;
- and
- a test signal generating circuit configured to generate the transmission signal for a test when receiving the test signal at an activated state at the test terminal, or to stop generating the transmission signal for the test when receiving the test signal at a non-activated state at the test terminal.
5 more elements
Dependencies are inferred from the claim text.