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US 9,069,042 B2Granted
Efficient apparatus and method for testing digital shadow logic around non-logic design structures
AssigneeFreescale Semiconductor, Inc.
InventorsRajesh Raina, Magdy S. Abadir, Darrell L. Carder
Life of this patent
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Abstract
A circuit for efficiently testing digital shadow logic (504, 514) in isolation from an associated non-logic design structure (510) includes a width and delay matched bypass circuit (520) coupled to receive an n-bit input from shadow logic (504) and to generate therefrom an m-bit test output which is selectively connected to replace an m-bit output to the shadow logic (514) from the non-logic design structure (510) in a shadow logic test mode, thereby flexibly emulating the non-logic design structure to allowing separate isolated tests on the shadow logic and on the non-logic design structure.
Claims20
A semiconductor device, comprising:
- a non-logic circuit block coupled to receive an n-bit input and to generate an m-bit output from the n-bit input after a first propagation delay;
- a shadow logic coupled to the non-logic circuit block for interfacing the non-logic circuit block with external circuitry by generating an n-bit input signal for selective connection to the n-bit input of the non-logic circuit block and by processing an m-bit output signal that may be selectively connected from the m-bit output of the non-logic circuit block to generate a shadow logic output;
- a test input control circuit for generating a multi-bit input test signal for the shadow logic with each bit of the multi-bit input test signal being independently controllable;
- a bypass circuit coupled to receive the n-bit input in a shadow logic test mode and to generate an m-bit test output from the n-bit input with each bit of the m-bit test output from the bypass circuit being independently controllable, where the bypass circuit comprises delay matching circuitry for matching the first propagation delay of the non-logic circuit block;
- and
- a signal selection circuit coupled to the non-logic circuit block, bypass circuit, and shadow logic for selectively passing the m-bit output to the shadow logic in a first mode and passing the m-bit test output to the shadow logic in the shadow logic test mode.
3 more elements
A method comprising:
- providing a first test input to upstream digital shadow logic which generates an n-bit output for input to a memory block;
- selectively connecting the n-bit output to a memory block matching bypass circuit for emulating the memory block in a shadow logic test mode;
- processing the n-bit output at the memory block matching bypass circuit to generate an m-bit test output from at least the n-bit output, where each bit of the m-bit test output from the memory block matching bypass circuit is independently controllable and delay-matched to a propagation delay of the memory block;
- selectively connecting the m-bit test output to downstream digital shadow logic in the shadow logic test mode;
- and
- capturing a first test output from the downstream digital shadow logic which is generated independently of the memory block.
3 more elements
A method comprising:
- calculating a controllability measure for each bit of an m-bit input signal to a downstream shadow logic circuit connected to receive the m-bit input signal from a non-logic circuit block;
- identifying the n least controllable bits of the m-bit input signal to the downstream shadow logic circuit using the controllability measure calculated for each bit of the m-bit input signal;
- selectively connecting n-bits generated by an upstream shadow logic circuit to the n least controllable bits of the m-bit input signal to the downstream shadow logic circuit, where the upstream shadow logic circuit is connected to provide an n-bit input signal to the non-logic circuit block;
- generating one or more tests for the upstream and downstream shadow logic circuits using the n-bits generated by an upstream shadow logic circuit and m-n outputs from the non-logic circuit block as inputs;
- creating a truth table with the n-bits generated by an upstream shadow logic circuit as inputs and m-n outputs from the non-logic circuit block as outputs;
- and
- synthesizing the truth table with logic to create a bypass logic block.
4 more elements
Dependencies are inferred from the claim text.