Self evaluation of system on a chip with multiple cores

An integrated circuit with a system on a chip (SoC) comprising:

• a plurality of microprocessor cores on the integrated circuit wherein each microprocessor core of the plurality of microprocessor cores is considered a local core with a plurality of neighboring cores, wherein each local core further comprises:
• a self test mechanism that executes at least one test on the local core and produces a local signature for the local core where the local signature characterizes the local core;
• and
• a self evaluation engine (SEE) that performs a core centric serial compare of the local signature by comparing the local signature with a pre-defined number of neighbor core signatures shifted from the plurality of neighboring cores to produce results for each compare, wherein the SEE evaluates the results for each compare against a threshold to determine a goodness value, wherein the goodness value for each of the plurality of cores is used to produce a partial good status for the integrated circuit.

An integrated circuit comprising:

• a plurality of cores wherein each of the plurality of cores is considered a local core with a plurality of neighboring cores, wherein each local core further comprises:
• a self test mechanism that executes at least one test on the local core and produces a local signature for the local core where the local signature characterizes the local core;
• a self evaluation engine (SEE) that compares the local signature with a plurality of neighbor core signatures produced by the plurality of neighboring cores to determine a goodness value for the local core;
• and
• wherein the SEE performs a parallel compare of the local signature with the plurality of neighbor core signatures produced by the plurality of neighboring cores.