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US 9,058,900 B2Granted
System, semiconductor memory device and operating method thereof
AssigneeSK hynix Inc.
InventorWon Kyung Kang
Life of this patent
Estimating the term…
Abstract
A method for operating a semiconductor memory device including a memory block constituted by first memory cells used as main memory cells and second memory cells includes reading out an erase count of the memory block stored in the second memory cells, erasing the memory block, increasing the read-out erase count, and storing the increased erase count in the second memory cells.
Claims16
A method for operating a semiconductor memory device including a memory block-constituted by main memory cells and dummy memory cells, the method comprising:
- reading out an erase count of the memory block stored in the dummy memory cells, erasing the memory block, increasing the read-out erase count, and storing the increased erase count in the dummy memory cells,
- wherein the dummy memory cells are connected to at least one dummy word line,
- wherein the main memory cells are divided into a main cell area and a flag cell area,
- wherein the dummy memory cells are divided into a dummy main cell area and a dummy flag cell area,
- wherein the erase count of the memory block is read out from the dummy flag cell area, and
- wherein the increased erase count is stored in the dummy flag cell area.
3 more elements
A semiconductor memory device comprising:
- a memory block including main memory cells and dummy memory cells;
- and
- a control logic configured to control an erase operation of the memory block,
- wherein the main memory cells are divided into a main cell area and a flag cell area,
- wherein the dummy memory cells are divided into a dummy main cell area and a dummy flag cell area,
- wherein the control logic reads out an erase count of the memory block stored in the dummy flag cell area, erases the memory block, increases the read-out erase count, and stores the increased erase count to the dummy flag cell area, and
- wherein the dummy memory cells are connected to at least one dummy word line.
4 more elements
A system comprising:
- a memory block including main memory cells and dummy memory cells;
- and
- a control logic configured to control an erase operation of the memory block,
- wherein the main memory cells are divided into a main cell area and a flag cell area,
- wherein the dummy memory cells are divided into a dummy main cell area and a dummy flag cell area,
- wherein the control logic reads out an erase count of the memory block stored in the dummy flag cell area, erases the memory block, increases the read-out erase count, and stores the increased erase count to the dummy flag cell area, and
- wherein the dummy memory cells are connected to at least one dummy word line.
4 more elements
Dependencies are inferred from the claim text.