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US 9,054,695 B2Granted
Technique to realize high voltage IO driver in a low voltage BiCMOS process
AssigneeTexas Instruments Incorporated
InventorsSamiran Dasgupta, Devraj Matharampallil Rajagopal
Life of this patent
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Abstract
An IO circuit capable of high voltage signaling in a low voltage BiCMOS process. The IO circuit includes a voltage rail generator circuit that receives a reference voltage and generates a voltage rail supply. A BJT (bi-polar junction transistor) buffer circuit is coupled to the voltage rail generator circuit and a pad. The BJT buffer circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit receives the voltage rail supply. The pull-down circuit is coupled to the pull-up circuit. The pad is coupled to the pull-up circuit and the pull-down circuit.
Claims20
An input/output (IO) circuit comprising:
- a voltage rail generator circuit configured to receive a reference voltage and configured to generate a voltage rail supply;
- a BJT (bi-polar junction transistor) buffer circuit coupled to the voltage rail generator circuit and a pad, wherein the BJT buffer circuit further comprises:
- a pull-up circuit configured to receive the voltage rail supply;
- a pull-down circuit coupled to the pull-up circuit, wherein the pad is coupled to the pull-up circuit and the pull-down circuit;
- a first base current supply circuit coupled to the pull-up circuit and configured to receive an input signal;
- and
- a second base current supply circuit coupled to the pull-down circuit and configured to receive the input signal and a core supply;
- a first charge injection circuit coupled to the pull-up circuit and configured to receive the input signal and the core supply;
- a second charge injection circuit coupled to the pull-down circuit and configured to receive the input signal and the core supply;
- and a blocking diode coupled between the pull-up circuit and the pull-down circuit.
7 more elements
A method comprising:
- generating a voltage rail supply from a reference voltage;
- injecting current in a second PNP transistor to activate the second PNP transistor when an input signal transitions from logic-LOW to logic-HIGH;
- configuring a first base current supply circuit to receive the input signal and provide current to the second PNP transistor after activation of the second PNP transistor;
- charging a pad to the supply rail voltage;
- injecting current in a second NPN transistor to activate the second NPN transistor when the input signal transitions from logic-HIGH to logic-LOW;
- configuring a second base current supply circuit to receive the input signal and provide current to the second NPN transistor after activation of the second NPN transistor;
- and
- discharging the pad to a ground voltage.
5 more elements
A computing device comprising:
- a processing unit;
- a memory module coupled to the processing unit;
- and
- a plurality of logic circuits coupled to the processing unit and the memory module;
- and
- an IO circuit coupled to atleast one logic circuit of the plurality of logic circuits, the IO circuit comprising:
- a voltage rail generator circuit configured to receive a reference voltage and configured to generate a voltage rail supply;
- a BJT (bi-polar junction transistor) buffer circuit coupled to the voltage rail generator circuit and a pad, wherein the BJT buffer circuit further comprises:
- a second PNP transistor configured to receive the voltage rail supply;
- a second NPN transistor coupled to the second PNP transistor, wherein the pad is coupled to the second PNP transistor and the second NPN transistor;
- a first base current supply circuit and a first charge injection circuit coupled to the second PNP transistor, wherein the first base current supply circuit and the first charge injection circuit are configured to receive an input signal;
- a second base current supply circuit and a second charge injection circuit coupled to the second NPN transistor, wherein the second base current supply circuit and the second charge injection circuit are configured to receive the input signal, and the first charge injection circuit and the second charge injection circuit configured to receive a core supply;
- and
- a blocking diode coupled between the second PNP transistor and the second NPN transistor.
11 more elements
Dependencies are inferred from the claim text.