# US 9,049,807 B2 · Processes of making pad-less interconnect for electrical coreless substrate

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- Number: US 9,049,807 B2
- Document ID: US9049807B2
- Status: Granted
- Kind: B2
- Application number: 12/215,018
- Filed: 2008-06-24
- Published: 2009-12-24
- Granted: 2015-06-02
- Earliest claimed: 2008-06-24
- Assignees: Intel Corporation
- Applicants: Javier Soto; Charan Gurumurthy; Robert Nickerson; Debendra Mallik
- Inventors: Javier Soto; Charan Gurumurthy; Robert Nickerson; Debendra Mallik
- Web page: https://patentgrep.com/patent/US9049807B2

## CPC

- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H05K 3/4007: {Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465)}
- H05K 3/4682: {Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H05K 1/113: {Via provided in pad; Pad over filled via}
- H05K 3/0035: {of blind holes, i.e. having a metal layer at the bottom}
- H05K 3/007: {Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier (H05K1/187, H05K3/20 and H05K3/4682 take precedence)}
- H05K 3/20: by affixing prefabricated conductor pattern {(H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence)}
- H05K 3/244: {Finish plating of conductors, especially of copper conductors, e.g. for pads or lands (selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3465)}
- H05K 3/28: Applying non-metallic protective coatings {(H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673)}
- H05K 3/3465: Application of solder
- H05K 2201/0367: Metallic bump or raised conductor not used as solder bump
- H05K 2201/096: Vertically aligned vias, holes or stacked vias
- H05K 2203/0152: Temporary metallic carrier, e.g. for transferring material
- H05K 2203/1536: Temporarily stacked PCBs
- H10W 72/07254: {changes in dispositions}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/90: Bond pads, in general
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 29/49147: Assembling terminal to base
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.

## Claims

### Claim 1

A process comprising:
providing a mounting substrate, wherein the mounting substrate includes a central core, a center metallic substrate layer embedded in the central core, and a metallic substrate layer adjacent the center metallic substrate layer;
forming a first dielectric layer on the metallic substrate layer, wherein the first dielectric layer has a die side adjacent the metallic substrate layer and an opposing land side;
forming a recess through the first dielectric layer to expose a fraction of the metallic substrate layer;
forming a surface finish first layer on the fraction of the metallic substrate layer that is exposed through the recess;
forming an electrically conductive first plug within the recess;
separating the center metallic substrate layer and central core from the metallic substrate layer;
removing the metallic substrate layer, wherein removing the metallic substrate layer exposes the surface finish first layer and wherein the exposed surface finish first layer is planar to the first dielectric layer die side; and
forming an electrical connector electrically coupled to the electrically conductive first plug proximate the first dielectric layer die side, after removing the metallic substrate layer.

### Claim 2 (depends on 1)

The process of claim 1, further including:
forming a surface finish second layer on the surface finish first layer;
and
wherein forming the electrical connector electrically coupled to the conductive first plug includes forming the electrical connector on the surface finish first layer.

### Claim 3 (depends on 1)

The process of claim 1, wherein forming the recess is carried out by radiant energy ablation to form a characteristic recess dimension.

### Claim 4 (depends on 1)

The process of claim 1, wherein the metallic substrate layer is a first side metallic substrate layer disposed proximate a first side of the central core, and further including a second center metallic substrate layer adjacent a second side of the central core, and a second side metallic substrate layer disposed adjacent the second center metallic substrate layer embedded in the central core, the process further including:
forming a second side first dielectric layer on the second side metallic substrate layer, wherein the second side first dielectric layer includes a die side adjacent the second side metallic substrate layer and an opposing land side;
forming a second recess through the second dielectric layer to expose a fraction of the second side metallic substrate layer;
forming a surface finish first film on the fraction of the metallic substrate layer that is exposed through the second recess, wherein the surface first film is planar to the second dielectric layer die side;
forming an electrically conductive plug within the second recess; and
separating the center metallic substrate layer, the second center metallic substrate layer, and the central core from the first side metallic substrate layer and the second side metallic substrate layer.

### Claim 5 (depends on 1)

The process of claim 1, wherein forming the recess is carried out by radiant energy ablation to form a characteristic recess dimension, the process further including:
forming a surface finish second film on the surface finish first film;
wherein forming the electrical connector electrically coupled to the conductive first plug includes forming the electrical connector on the surface finish first film.

### Claim 6 (depends on 1)

The process of claim 1, further including mating a microelectronic die to the electrical connector.

### Claim 7 (depends on 1)

The process of claim 1, further including:
forming an electrically conductive subsequent plug disposed proximate the first dielectric layer land side, wherein the electrically conductive subsequent plug is electrically coupled to the electrically conductive first plug, and disposed directly above the electrically conductive first plug; and
mating a microelectronic die to the electrical connector.

### Claim 8

A process comprising:
providing a mounting substrate, wherein the mounting substrate includes a central core, a center metallic substrate layer embedded in the central core, and a metallic substrate layer adjacent the center metallic substrate layer;
forming a first dielectric layer on the metallic substrate layer, wherein the first dielectric layer has a die side adjacent the metallic substrate layer and an opposing land side;
forming a recess through the first dielectric layer to expose a fraction of the metallic substrate layer;
forming at least one surface finish layer in the recess and upon the metallic substrate layer, wherein the at least one surface finish layer is planar to the first dielectric layer die side;
forming an electrically conductive first plug within the recess in contact with the at least one surface finish layer;
forming an electrically conductive subsequent plug disposed proximate the first dielectric layer land side, wherein the electrically conductive subsequent plug is electrically coupled to the electrically conductive first plug, and disposed directly above the electrically conductive first plug;
separating the center metallic substrate layer and central core from the metallic substrate layer;
removing the metallic substrate layer; and
forming an electrical connector in contact with the at least one surface finish layer, after removing the metallic substrate layer.

### Claim 9 (depends on 8)

The process of claim 8, wherein forming the recess is accomplished by laser ablation to achieve a characteristic dimension, and wherein forming the electrical connector is carried out within the characteristic dimension.

### Claim 10 (depends on 8)

The process of claim 8, further including:
electrically coupling the electrically conductive subsequent plug through the electrically conductive first plug; and
mating a microelectronic die to the electrically conductive first plug through the at least one surface finish film, and wherein mating includes mating the electrical connector disposed on the at least one surface finish layer to an electrical connector solder bump on the microelectronic die.

### Claim 11 (depends on 8)

The process of claim 8, further including:
electrically coupling the electrically conductive subsequent plug through the electrically conductive first plug; and
mating a microelectronic die to the electrically conductive first plug through the at least one surface finish film, and wherein mating includes mating the electrical connector disposed on the microelectronic die to the at least one surface finish film.

### Claim 12 (depends on 8)

The process of claim 8, further including:
electrically coupling the electrically conductive subsequent plug through the electrically conductive first plug; and
mating a microelectronic die to the electrically conductive first plug through the at least one surface finish film, and wherein mating includes mating the electrical connector disposed on the at least one surface finish layer to a bond pad on the microelectronic die.

### Claim 13

A process comprising:
providing a mounting substrate, wherein the mounting substrate includes a central core, a center metallic substrate layer embedded in the central core, and a metallic substrate layer adjacent the center metallic substrate layer;
forming a first dielectric layer on the metallic substrate layer, wherein the first dielectric layer has a die side adjacent the metallic substrate layer and an opposing land side;
forming a recess through the first dielectric layer to expose a fraction of the metallic substrate layer;
forming an in situ surface finish first layer on the fraction of the metallic substrate layer that is exposed through the recess, wherein the surface finish first layer is planar to the first dielectric layer die side;
forming an in situ surface finish second layer on the surface finish first layer;
forming an electrically conductive first plug within the recess in contact with the surface finish second layer and coupled to the metallic substrate layer;
forming an electrically conductive second plug in contact with the electrically conductive first plug;
forming an electrically conductive subsequent plug that is coupled to the electrically conductive second plug;
separating the center metallic substrate layer and central core from the metallic substrate layer;
removing the metallic substrate layer; and
forming an electrical connector electrically in contact with the surface finish first layer and coupled to the electrically conductive first plug proximate the first dielectric layer die side, after removing the metallic substrate layer.

### Claim 14 (depends on 13)

The process of claim 13, wherein forming the recess is carried out by radiant energy ablation to form a characteristic recess dimension.

### Claim 15 (depends on 13)

The process of claim 13, wherein the metallic substrate layer is a first side metallic substrate layer disposed proximate a first side of the central core, and further including a second center metallic substrate layer embedded in a second side of the central core, and a second side metallic substrate layer disposed adjacent the second center substrate layer, the process further including:
forming a second side first dielectric layer on the second side metallic substrate layer, wherein the second side first dielectric layer includes a die side adjacent the second side metallic substrate layer and an opposing land side;
forming a second recess through the second dielectric layer to expose a fraction of the second side metallic substrate layer;
forming a surface finish first layer on the fraction of the metallic substrate layer that is exposed through the second recess, wherein the surface first layer is planar to the second dielectric layer die side;
forming an electrically conductive first plug within the second recess;
forming an electrically conductive second plug in contact with the electrically conductive first plug coupled to the second side metallic substrate;
forming an electrically conductive subsequent plug that is coupled to the electrically conductive second plug; and
separating the center metallic substrate layer, the second center metallic substrate layer, and the central core from the first side metallic substrate layer and the second side metallic substrate layer.

### Claim 16 (depends on 13)

The process of claim 13, further including mating a microelectronic die to the electrical connector.

### Claim 17

A process comprising:
providing a mounting substrate, wherein the mounting substrate includes a central core, a center metallic substrate layer embedded in the central core, and a metallic substrate layer adjacent the center metallic substrate layer;
forming a first dielectric layer on the metallic substrate layer, wherein the first dielectric layer has a die side adjacent the metallic substrate layer and an opposing land side;
forming a recess through the first dielectric layer to expose a fraction of the metallic substrate layer by laser ablation to achieve a characteristic dimension;
forming at least one surface finish layer in the recess and upon the metallic substrate layer, wherein the at least one surface finish first layer is planar to the first dielectric layer die side;
forming an electrically conductive first plug within the recess in contact with the at least one surface finish layer;
forming an electrically conductive second plug disposed on the land side and in contact with the electrically conductive first plug;
forming an electrically conductive subsequent plug disposed on the land side, wherein the electrically conductive subsequent plug is electrically coupled to the electrically conductive second plug, and disposed directly above the electrically conductive second plug;
separating the center metallic substrate layer and central core from the metallic substrate layer;
removing the metallic substrate layer; and
forming an electrical connector in contact with the at least one surface finish layer, wherein forming the electrical connector is carried out within the characteristic dimension, after removing the metallic substrate layer.

### Claim 18 (depends on 17)

The process of claim 17, further including:
mating a microelectronic die to the electrically conductive first plug through the at least one surface finish film, and wherein mating includes mating the electrical connector disposed on the microelectronic die to the at least one surface finish film.

### Claim 19 (depends on 17)

The process of claim 17, further including:
electrically coupling the electrically conductive subsequent plug through the electrically conductive first plug; and
mating a microelectronic die to the electrically conductive first plug through the at least one surface finish film, and wherein mating includes mating the electrical connector disposed on the at least one surface finish layer to a bond pad on the microelectronic die.