Memory system having memory ranks and related tuning method
AssigneeSamsung Electronics Co., Ltd.
InventorsEunsung Seo, Chul-Sung Park, Chi-Sung Oh
Life of this patent
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Abstract
A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.
Claims11
A memory device, comprising:
- at least two memory ranks sharing input/output lines,
- at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines;
- a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals;
- and
- at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.
Dependencies are inferred from the claim text.