Racetrack memory with electric-field assisted domain wall injection for low-power write operation
AssigneeInternational Business Machines Corporation
InventorsAnthony J. Annunziata, Marcin J. Gajek
Life of this patent
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Abstract
Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization direction in the nanowire.
Claims18
A method for injecting domain walls in a magnetic racetrack memory comprising:
- coupling a racetrack comprising a nanowire with a gate in order to manipulate an anisotropy associated with the nanowire;
- and
- coupling the racetrack and gate with a pinning layer configured to establish a magnetization direction in the nanowire;
- wherein the pinning layer comprises antiferromagnetic material;
- wherein the gate comprises a nonmagnetic metal electrode adjacent to a dielectric layer;
- wherein the pinning layer and the gate are disposed on opposite sides of the nanowire, such that the nanowire is sandwiched in between the pinning layer and the gate.
A computer program product for injecting domain walls in a magnetic racetrack memory, the computer program product comprising a non-transitory computer readable storage medium having program code embodied therewith, the program code executable by a device to:
- couple a racetrack comprising a nanowire with a gate in order to manipulate an anisotropy associated with the nanowire;
- and
- couple the racetrack and gate with a pinning layer configured to establish a magnetization direction in the nanowire;
- wherein the pinning layer comprises antiferromagnetic material;
- wherein the gate comprises a nonmagnetic metal electrode adjacent to a dielectric layer;
- wherein the pinning layer and the gate are disposed on opposite sides of the nanowire, such that the nanowire is sandwiched in between the pinning layer and the gate.
A magnetic domain wall shift register memory comprising:
- a magnetic nanowire;
- a dielectric layer configured to provide a surface anisotropy contribution to the magnetic nanowire;
- at least one antiferromagnet configured to induce an exchange bias locally on the magnetic nanowire, wherein the at least one antiferromagnet is a pinning layer;
- a tunnel junction configured to provide a readout of a magnetic domain;
- and
- a gate disposed on the magnetic nanowire;
- wherein the gate comprises a nonmagnetic metal electrode adjacent to the dielectric layer;
- wherein the pinning layer and the gate are disposed on opposite sides of the magnetic nanowire, such that the magnetic nanowire is sandwiched in between the pinning layer and the gate.
Dependencies are inferred from the claim text.