Pulse generation circuit and semiconductor device

A pulse generation circuit, which includes a single conductivity type transistor, comprising:

• k (k is an integer of 2 or more)-stage first unit circuits connected in cascade;
• and
• k second unit circuits in each of which an input is connected to one of the first unit circuits and an output is connected to M (M is an integer of 2 or more) first wirings,
• the first unit circuit comprising:
• a second wiring to which a first voltage is input;
• a third wiring to which a second voltage lower than the first voltage is input;
• a first node, a second node, a third node, and a fourth node;
• a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal outputting voltage changes in the first node, the second node, the third node, and the fourth node as a first signal, a second signal, a third signal, and a fourth signal, respectively;
• a first input terminal and a second input terminal to which a first control signal and a second control signal are input, respectively;
• a third input terminal to which a third signal generated in the first unit circuit in a previous stage is input;
• a fourth input terminal to which a fourth signal generated in the first unit circuit in a next stage is input;
• a first transistor which connects the first node and the second wiring and a gate of which is connected to the third input terminal;
• a second transistor which connects the first node and the third wiring and a gate of which is connected to the second node;
• a third transistor which connects the second node and the second wiring and a gate of which is connected to the fourth input terminal;
• a fourth transistor which connects the second node and the third wiring and a gate of which is connected to the third input terminal;
• a fifth transistor which connects the fourth node and the first input terminal and a gate of which is connected to the first node;
• a sixth transistor which connects the fourth node and the third wiring and a gate of which is connected to the second node;
• a seventh transistor which connects the third node and the second input terminal and a gate of which is connected to the first node;
• and
• an eighth transistor which connects the third node and the third wiring and a gate of which is connected to the second node,
• the second unit circuits each comprising M third unit circuits to which different M control signals are input, and
• the third unit circuit comprising:
• the third wiring to which the second voltage is input;
• a fifth input terminal to which the first signal is input from the first unit circuit;
• a sixth input terminal to which the second signal is input from the first unit circuit;
• a seventh input terminal to which any one of the M control signals is input;
• a fifth output terminal to which any one of the M first wirings is connected;
• a ninth transistor which connects the fifth output terminal and the fifth input terminal and a gate of which is connected to the fifth input terminal;
• and
• a tenth transistor which connects the fifth output terminal and the third wiring and a gate of which is connected to the sixth input terminal.

A semiconductor device comprising:

• 2kMN pixel circuits (k, M, and N are each an integer of 2 or more) which are arranged in an array of 2kM rows and N columns;
• N source lines to which the pixel circuits in the same columns are connected and to each of which a source signal is input;
• a first gate driver and a second gate driver which each generate a gate signal for selecting the pixel circuit to which the source signal is input;
• and
• 2kM gate lines to which the pixel circuits in the same rows are connected and to each of which the gate signal is input,
• wherein the 2kM gate lines are alternately connected to the first gate driver and the second gate driver in every M rows,
• the first gate driver and the second gate driver each comprising:
• a single conductivity type transistor;
• a shift register including k-stage first unit circuits connected in cascade;
• and
• k second unit circuits in each of which an input is connected to one of the first unit circuits and an output is connected to M wirings,
• wherein one of the first unit circuits comprises a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal,
• wherein the one of the first unit circuits is configured to output a first signal from the first output terminal to a previous stage of the one of the first unit circuits,
• wherein the one of the first unit circuits is configured to output a second signal from the second output terminal to a next stage of the one of the first unit circuits,
• wherein the one of the first unit circuits is configured to output a third signal from the third and fourth output terminals to one of the second unit circuits in accordance with a fourth signal input from the previous stage of the one of the first unit circuits,
• wherein each of the second unit circuits has a function of dividing an output signal from each of the first unit circuits into M signals in accordance with M control signals and outputting the M signals to the M wirings as the gate signals.