# US 9,041,068 B2 · 3D semiconductor device and 3D logic array structure thereof

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- Number: US 9,041,068 B2
- Document ID: US9041068B2
- Status: Granted
- Kind: B2
- Application number: 14/042,776
- Filed: 2013-10-01
- Published: 2015-04-02
- Granted: 2015-05-26
- Earliest claimed: 2013-10-01
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Shih-Hung Chen
- Web page: https://patentgrep.com/patent/US9041068B2

## CPC

- H10D 84/903: {comprising field effect technology}
- H10D 84/907: {CMOS gate arrays}
- H03K 19/17704: the logic functions being realised by the interconnection of rows and columns
- H10B 12/50: {Peripheral circuit region structures}
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A 3D semiconductor device and a 3D logic array structure thereof are provided. The 3D semiconductor device includes an array structure, a periphery line structure and a 3D logic array structure. The array structure has Y contacts located at a side of the array structure. Y is within MN-1 to MN. Y, M and N are natural numbers. M is larger or equal to 2. The 3D logic array structure includes N sets of gate electrodes, an input electrode and Y output electrodes. Each set of the gate electrodes has M gate electrodes. The Y output electrodes connect the Y contacts. The M·N gate electrodes and the input electrode connect the periphery line structure.

## Claims

### Claim 1

A 3D logic array structure, comprising:
N sets of gate electrodes, wherein each set of the gate electrodes has M gate electrodes;
an input electrode; and
Y output electrodes, wherein the Y output electrodes connect Y contacts of an array structure, the Y contacts are located at a side of the array structure, the M·N gate electrodes and the input electrode connect a periphery line structure, Y is within MN-1 to MN, Y, M and N are natural numbers, and M is larger or equal to 2.

### Claim 2 (depends on 1)

The 3D logic array structure according to claim 1, wherein M is 2 and the logic values of two of each set of the gate electrodes are reverse.

### Claim 3 (depends on 1)

The 3D logic array structure according to claim 1, wherein M is larger than 2 and the logic values of M of each set of the gate electrodes are exclusive.

### Claim 4 (depends on 1)

The 3D logic array structure according to claim 1, wherein each output electrode connects one of each set of the gate electrodes.

### Claim 5 (depends on 1)

The 3D logic array structure according to claim 1, wherein the 3D logic array structure is a TFT AND gate array structure.

### Claim 6 (depends on 1)

The 3D logic array structure according to claim 1, wherein the 3D logic array structure is a double gate array structure.

### Claim 7 (depends on 1)

The 3D logic array structure according to claim 1, wherein the 3D logic array structure is a single gate array structure.