# US 9,041,067 B2 · Integrated half-bridge circuit with low side and high side composite switches

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- Number: US 9,041,067 B2
- Document ID: US9041067B2
- Status: Granted
- Kind: B2
- Application number: 14/168,926
- Filed: 2014-01-30
- Published: 2014-08-14
- Granted: 2015-05-26
- Earliest claimed: 2013-02-11
- Assignees: International Rectifier Corporation
- Applicants: International Rectifier Corporation
- Inventors: Michael A. Briere
- Web page: https://patentgrep.com/patent/US9041067B2

## CPC

- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H03K 17/107: {in composite switches}
- H03K 17/567: Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
- H10D 84/05: using Group III-V technology
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D 84/82: of only field-effect components
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/101: {comprising components on opposite major surfaces of semiconductor substrates}
- H03K 2017/6875: {using self-conductive, depletion FETs}
- H10D 84/01: Manufacture or treatment
- H10D 84/0158: {the components including FinFETs}
- H10D 84/84: Combinations of enhancement-mode IGFETs and depletion-mode IGFETs
- H10W 90/752: {between stacked chips}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

There are disclosed herein various implementations of an integrated half-bridge circuit with low side and high side composite switches. In one exemplary implementation, such an integrated half-bridge circuit includes a III-N body including first and second III-N field-effect transistors (FETs) monolithically integrated with and situated over a first group IV FET. The integrated half-bridge circuit also includes a second group IV FET stacked over the III-N body. The first group IV FET is cascoded with the first III-N FET to provide one of the low side and the high side composite switches, and the second group IV FET is cascoded with the second III-N FET to provide the other of the low side and the high side composite switches. The first and second III-N FETs are normally ON FETs, and the low side composite switch and the high side composite switch are normally OFF switches

## Claims

### Claim 1

An integrated half-bridge circuit including a low side composite switch and a high side composite switch, said integrated half-bridge circuit comprising:
a III-N body including first and second III-N field-effect transistors (FETs) monolithically integrated with and situated over a first group IV FET;
a second group IV FET stacked over said III-N body;
said first group IV FET cascoded with said first III-N FET to provide one of said low side and said high side composite switches, and said second group IV FET cascoded with said second III-N FET to provide the other of said low side and said high side composite switches;
wherein said first and second III-N FETs are normally ON FETs, and wherein said low side composite switch and said high side composite switch are normally OFF switches.

### Claim 2 (depends on 1)

The integrated half-bridge circuit of claim 1, wherein a source of said first III-N FET is coupled to a drain of said first group IV FET by a through-semiconductor via (TSV) through said III-N body.

### Claim 3 (depends on 1)

The integrated half-bridge circuit of claim 1, wherein a drain of said second group IV FET on a bottom side of said second group IV FET is stacked on a source of said second III-N FET.

### Claim 4 (depends on 1)

The integrated half-bridge circuit of claim 1, wherein said first group IV FET, said second group IV FET, and said first and second III-N FETs are monolithically integrated.

### Claim 5 (depends on 1)

The integrated half-bridge circuit of claim 1, wherein at least one of said first and second group IV FETs comprises a lateral channel FET.

### Claim 6 (depends on 1)

The integrated half-bridge circuit of claim 1, wherein at least one of said first and second group IV FETs comprises a vertical channel FET.

### Claim 7 (depends on 1)

The integrated half-bridge circuit of claim 1, wherein said first and second group IV FETs comprise low-voltage silicon FETs.

### Claim 8 (depends on 1)

The integrated half-bridge circuit of claim 1, wherein said first and second III-N FETs comprise high-voltage III-N FETs.

### Claim 9 (depends on 1)

The integrated half-bridge circuit of claim 1, wherein said first and second III-N FETs comprise III-N high electron mobility transistors (HEMTs).

### Claim 10

An integrated half-bridge circuit including a low side composite switch and a high side composite switch, said integrated half-bridge circuit comprising:
a first group IV field-effect transistor (FET) stacked under a substrate;
a III-N body including first and second III-N FETs situated over said substrate;
a second group IV FET stacked over said III-N body;
said first group IV FET cascoded with said first III-N FET to provide one of said low side and said high side composite switches, and said second group IV FET cascoded with said second III-N FET to provide the other of said low side and said high side composite switches;
wherein said first and second III-N FETs are normally ON FETs, and wherein said low side composite switch and said high side composite switch are normally OFF switches.

### Claim 11 (depends on 10)

The integrated half-bridge circuit of claim 10, wherein said first III-N FET is coupled to said first group IV FET by a through-semiconductor via (TSV).

### Claim 12 (depends on 10)

The integrated half-bridge circuit of claim 10, wherein said TSV extends through said substrate and contacts a drain of said first group IV FET.

### Claim 13 (depends on 10)

The integrated half-bridge circuit of claim 10, wherein a drain of said second group IV FET on a bottom side of said second group IV FET is stacked on a source of said second III-N FET.

### Claim 14 (depends on 10)

The integrated half-bridge circuit of claim 10, wherein said first and second III-N FETs are monolithically integrated.

### Claim 15 (depends on 10)

The integrated half-bridge circuit of claim 10, wherein said first and second group IV FETs comprise silicon FETs.

### Claim 16 (depends on 10)

The integrated half-bridge circuit of claim 10, wherein said first and second group IV FETs comprise low-voltage group IV FETs, and wherein said first and second III-N FETs comprise high-voltage III-N FETs.

### Claim 17 (depends on 10)

The integrated half-bridge circuit of claim 10, wherein said first and second III-N FETs comprise III-N high electron mobility transistors (HEMTs).

### Claim 18 (depends on 10)

The integrated half-bridge circuit of claim 10, wherein said first and second III-N FETs and one of said first and second group IV FETs are monolithically integrated.

### Claim 19 (depends on 10)

The integrated half-bridge circuit of claim 10, wherein at least one of said first and second group IV FETs comprises a lateral channel FET.

### Claim 20 (depends on 10)

The integrated half-bridge circuit of claim 10, wherein at least one of said first and second group IV FETs comprises a vertical channel FET.