# US 9,041,064 B2 · High voltage GaN transistor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,041,064 B2 - Document ID: US9041064B2 - Status: Granted - Kind: B2 - Application number: 13/445,632 - Filed: 2012-04-12 - Published: 2012-09-06 - Granted: 2015-05-26 - Earliest claimed: 2006-11-21 - Assignees: Cree, Inc. - Applicants: Yifeng Wu; Primit Parikh; Umesh Mishra - Inventors: Yifeng Wu; Primit Parikh; Umesh Mishra - Web page: https://patentgrep.com/patent/US9041064B2 ## CPC - H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs} - H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT} - H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D 64/112: {comprising multiple field plate segments} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A multiple field plate transistor includes an active region, with a source, drain, and gate. A first spacer layer is between the source and the gate and a second spacer layer between the drain and the gate. A first field plate on the first spacer layer and a second field plate on the second spacer layer are connected to the gate. A third field plate connected to the source is on a third spacer layer, which is on the gate and the first and second field plates and spacer layers. The transistor exhibits a blocking voltage of at least 600 Volts while supporting current of at least 2 or 3 Amps with on resistance of no more than 5.0 or 5.3 mΩ-cm2, respectively, and at least 900 Volts while supporting current of at least 2 or 3 Amps with on resistance of no more than 6.6 or 7.0 mΩ-cm2, respectively. ## Claims ### Claim 1 A transistor device, comprising: an active region; source and drain electrodes in electrical contact with said active region; a gate electrode between said source and drain electrodes and in electrical contact with said active region; a plurality of field plates on said active region, wherein a first of said field plates is integral with said gate electrode and extends toward said source electrode and a second of said field plates is integral with said gate electrode extending toward said drain electrode, said first field plate extending a greater distance toward said source electrode than said second field plate extends toward said drain electrode without contacting said source electrode; and wherein said field plates are configured such that the transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps. ### Claim 2 (depends on 1) The transistor of claim 1, comprising an on resistance of less than 5.0 mΩ-cm2. ### Claim 3 (depends on 1) The transistor of claim 1, supporting a current of at least 3 Amps with an on resistance of less than 5.3 mΩ-cm2. ### Claim 4 (depends on 1) The transistor of claim 1, further comprising an insulating layer below each of said field plates. ### Claim 5 (depends on 1) The transistor of claim 1, further comprising a plurality of insulating spacer layers, a first of said spacer layers interposed between a first of said field plates and said active region, others of said spacer layers on said first field plate. ### Claim 6 (depends on 1) The transistor of claim 1, wherein at least one of said field plates is electrically connected to said gate electrode structure. ### Claim 7 (depends on 5) The transistor of claim 5, wherein a first one of said field plates is integral to said gate electrode and extends on said first spacer layer toward said source electrode, and wherein at least one field plate is connected to said source electrode. ### Claim 8 (depends on 1) The transistor device of claim 1, wherein an outermost of said field plates is farthest from said gate electrode, said outermost field plate electrically connected to said source electrode. ### Claim 9 (depends on 8) The transistor device of claim 8, wherein said outermost field plate is electrically connected to said source through at least one conductive bus extending from said outermost field plate to said source electrode. ### Claim 10 (depends on 8) The transistor device of claim 8, wherein said outermost field plate is connected to said source through a conductive bus, at least a portion of said conductive bus external to the footprint of said active region. ### Claim 11 (depends on 7) The transistor device of claim 7, wherein a second of said field plates is integral to said gate electrode and extends on said first spacer layer toward said drain. ### Claim 12 A transistor device, comprising: an active region; source and drain electrodes in electrical contact with said active region; a gate electrode comprising a gate length, said gate electrode between said source and drain electrodes and in electrical contact with said active region; a plurality of field plates on said active region, wherein a first of said field plates is integral with said gate electrode and extends toward said source electrode a distance equal to or longer than said gate length and a second of said field plates is integral with said gate electrode extending toward said drain electrode, said first field plate extending a greater distance toward said source electrode than said second field plate extends toward said drain electrode without contacting said source electrode; and wherein said field plates are configured such that transistor exhibits a blocking voltage of at least 900 Volts while supporting a current of at least 2 Amps. ### Claim 13 (depends on 12) The transistor device of claim 12, comprising an on resistance of less than 6.6 mΩ-cm2. ### Claim 14 (depends on 12) The transistor device of claim 12, exhibiting a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of less than 7.0 mΩ-cm2. ### Claim 15 A transistor, comprising: an active region; source and drain electrodes in electrical contact with said active region; a gate electrode between said source and drain electrodes and in electrical contact with said active region; a plurality of field plates on said active region, a first and second of said field plates integral with said gate electrode and extending toward said source and drain electrodes respectively, wherein said first field plate is longer than said second field plate and does not contact said source electrode; and an outermost field plate of said plurality of field plates that is farthest from said gate electrode is electrically connected to said source electrode. ### Claim 16 (depends on 15) The transistor of claim 15, further comprising a plurality of insulating spacer layers, a first of said spacer layers interposed between a first of said field plates and said active region, others of said spacer layers on said first field plate to isolate others of said field plates from the layers below. ### Claim 17 (depends on 15) The transistor of claim 15, exhibiting a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of less than 5.0 mΩ-cm2. ### Claim 18 (depends on 15) The transistor of claim 15, exhibiting a blocking voltage of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of less than 5.3 mΩ-cm2. ### Claim 19 (depends on 15) The transistor of claim 15, exhibiting a blocking voltage of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of less than 6.6 mΩ-cm2. ### Claim 20 (depends on 15) The transistor of claim 15, exhibiting a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of less than 7.0 mΩ-cm2. ### Claim 21 (depends on 15) The transistor of claim 15, further comprising a high electron mobility transistor.