# US 9,041,062 B2 · Silicon-on-nothing FinFETs

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- Number: US 9,041,062 B2
- Document ID: US9041062B2
- Status: Granted
- Kind: B2
- Application number: 14/031,502
- Filed: 2013-09-19
- Published: 2015-03-19
- Granted: 2015-05-26
- Earliest claimed: 2013-09-19
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Ali Khakifirooz; Alexander Reznicek; Dominic J. Schepis
- Web page: https://patentgrep.com/patent/US9041062B2

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 50/642: {Chemical etching}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P 50/242: {of Group IV materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes an insulator formed within a void to electrically isolate a fin from an underlying substrate. The void is created by removing a doped sacrificial layer formed between the substrate and a fin layer. The sacrificial layer is doped to allow for a thicker layer relative to an un-doped layer of substantially similar composition. The doped sacrificial layer thickness may be between 10 nm and 250 nm and may be carbon doped silicon-germanium. The thicker sacrificial layer allows for a thicker insulator so as to provide adequate electrical isolation between the fin and the substrate. During formation of the void, the fin may be supported by a dummy gate. The semiconductor structure may also include a bulk region that has at least a maintained portion of the doped sacrificial layer.

## Claims

### Claim 1

A method of fabricating a semiconductor device, the method comprising:
forming an epitaxial carbon doped silicon germanium (SiGe:C) sacrificial portion upon a substrate;
forming a fin portion upon the SiGe:C sacrificial portion;
creating a void by removing the SiGe:C sacrificial portion between the substrate and the fin portion, and;
forming an insulator within the void, the insulator electrically isolating the fin portion from the substrate.

### Claim 2 (depends on 1)

The method of claim 1 wherein the fin portion is epitaxial silicon.

### Claim 3 (depends on 1)

The method of claim 1 wherein the SiGe:C sacrificial portion is doped to allow for a thicker sacrificial portion relative to an un-doped sacrificial portion of substantially similar composition.

### Claim 4 (depends on 1)

The method of claim 1 further comprising:
forming a dummy gate to support the fin portion prior to creating the void.

### Claim 5 (depends on 1)

The method of claim 1 wherein the SiGe:C sacrificial portion has a thickness between 10 and 250 nm.

### Claim 6 (depends on 1)

The method of claim 1 further comprising:
maintaining a bulk portion of the SiGe:C sacrificial layer in a bulk region.

### Claim 7 (depends on 2)

The method of claim 2 wherein forming the SiGe:C sacrificial portion and forming the fin portion further comprises:
patterning a SiGe:C sacrificial layer formed upon the substrate and a epitaxial silicon layer formed upon the SiGe:C sacrificial layer.

### Claim 8

A semiconductor device comprising:
an epitaxial carbon doped silicon germanium (SiGe:C) sacrificial layer upon a substrate upon, and;
an insulator formed within a void that electrically isolates a fin from the substrate, wherein the void is formed by removing the sacrificial layer between the substrate and the fin.

### Claim 9 (depends on 8)

The semiconductor device of claim 8 further comprising:
an epitaxial silicon portion upon the epitaxial doped sacrificial layer.

### Claim 10 (depends on 8)

The semiconductor device of claim 8 wherein the doped sacrificial layer is doped to allow for a thicker sacrificial layer relative to an un-doped sacrificial layer of substantially similar composition.

### Claim 11 (depends on 8)

The semiconductor device of claim 8 further comprising:
a dummy gate that supports the fin.

### Claim 12 (depends on 8)

The semiconductor device of claim 8 wherein the doped sacrificial layer has a thickness between 10 and 250 nm.

### Claim 13 (depends on 8)

The semiconductor device of claim 8 further comprising:
a bulk region comprising at least a maintained portion of the doped sacrificial layer.

### Claim 14 (depends on 8)

The design structure of claim 8 further comprising:
a dummy gate that supports the fin.

### Claim 15 (depends on 8)

The design structure of claim 8 wherein the doped sacrificial layer has a thickness between 10 and 250 nm.

### Claim 16 (depends on 8)

The design structure of claim 8 further comprising:
a bulk region comprising at least a maintained portion of the doped sacrificial layer.

### Claim 17 (depends on 9)

The semiconductor device of claim 9 wherein the epitaxial SiGe:C sacrificial layer and the epitaxial silicon portion are patterned to form the fin.

### Claim 18

A design structure embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
an epitaxial carbon doped silicon germanium (SiGe:C) sacrificial layer upon a substrate upon, and;
an insulator formed within a void that electrically isolates a fin from the substrate, wherein the void is formed by removing the sacrificial layer between the substrate and the fin.

### Claim 19 (depends on 18)

The design structure of claim 18 further comprising:
an epitaxial silicon portion upon the epitaxial doped sacrificial layer.

### Claim 20 (depends on 18)

The design structure of claim 18 wherein the doped sacrificial layer is doped to allow for a thicker sacrificial layer relative to an un-doped sacrificial layer of substantially similar composition.