# US 9,041,061 B2 · III-V device with overlapped extension regions using replacement gate

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- Number: US 9,041,061 B2
- Document ID: US9041061B2
- Status: Granted
- Kind: B2
- Application number: 13/950,788
- Filed: 2013-07-25
- Published: 2015-01-29
- Granted: 2015-05-26
- Earliest claimed: 2013-07-25
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Amlan Majumdar; Yanning Sun
- Web page: https://patentgrep.com/patent/US9041061B2

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/4735: {having delta-doped or planar-doped donor layers}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/605: {Planar doped, e.g. atomic-plane doped or delta-doped}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 62/82: Heterojunctions
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a replacement gate process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having multiple layers and a T-shaped gate structure using a gate replacement process. The T-shaped gate structure may be formed with a bottom surface substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the III-V compound semiconductor-containing heterostructure. An undoped region may be formed below the bottom surface of the T-shaped gate structure on a layer of the III-V compound semiconductor-containing heterostructure.

## Claims

### Claim 1

A method of forming a semiconductor device, comprising the steps of:
forming a III-V compound semiconductor-containing heterostructure above a substrate, wherein the III-V compound semiconductor-containing heterostructure comprises a buffer layer above the substrate, a channel layer above and in contact with the buffer layer, a barrier layer above and in contact with the channel layer, and an etch stop layer above and in contact with the barrier layer;
forming gate spacers on an uppermost surface of the etch stop layer;
forming raised source-drain (RSD) regions on the uppermost surface of the etch stop layer, wherein the RSD regions are adjacent to and contacting the gate spacers;
forming a dielectric layer on the uppermost surface of the RSD regions, wherein the dielectric layer is adjacent to and contacting the gate spacers, and wherein an uppermost surface of the dielectric layer is higher than an uppermost surface of the gate spacers;
removing a portion of the etch stop layer and a portion of the barrier layer between the gate spacers to form an opening, wherein the opening exposes an uppermost surface of the channel layer; and
forming a T-shaped gate structure above the uppermost surface of the channel layer in the opening, wherein the T-shaped gate structure comprises:
a narrow bottom portion extending from the uppermost surface of the spacers to no further than a lowermost portion of the barrier layer, the narrow bottom portion having sidewalls that are substantially flush with sidewalls of the gate spacers, and
a wide upper portion that extends from the uppermost surface of the spacers to the uppermost surface of the dielectric layer, the wide upper portion having a lowermost surface only in contact with the uppermost surface of the gate spacers.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming a delta-doped region within the barrier layer by doping the region with an element from Group IV, II, or VI of the Periodic Table of Elements.

### Claim 3 (depends on 1)

The method of claim 1, wherein the upper portion of the T-shaped gate structure is laterally wider, by the combined width of the gate spacers, than the bottom portion of the T-shaped gate structure.

### Claim 4 (depends on 1)

The method of claim 1, further comprising forming an undoped region between the bottom portion of the T-shaped gate structure and the channel layer.

### Claim 5

A method of forming a semiconductor device, comprising the steps of:
forming a III-V compound semiconductor-containing heterostructure on a substrate, wherein the III-V compound semiconductor-containing heterostructure comprises a buffer layer above the substrate, a channel layer above and in contact with the buffer layer, a barrier layer above and in contact with the channel layer, and an etch stop layer above and in contact with the barrier layer;
forming a dummy gate on an uppermost surface of the etch stop layer;
forming a dummy gate hardmask on an uppermost surface of the dummy gate;
forming spacers on the uppermost surface of the etch stop layer, the spacers adjacent to and contacting the dummy gate and the dummy gate hardmask, wherein the spacers have an uppermost surface that is substantially flush with an upper surface of the dummy gate hardmask;
forming raised source-drain (RSD) regions on the uppermost surface of the etch stop layer, the RSD regions adjacent to and contacting the spacers;
forming a dielectric layer on an uppermost surface of the RSD regions, the dielectric layer adjacent to and contacting the spacers, wherein an uppermost surface of the dielectric layer is substantially flush with the uppermost surface of the spacers;
removing the dummy gate hardmask;
removing the dummy gate;
removing an upper portion of the spacers to form gate spacers, wherein an uppermost surface of the gate spacers is lower than the uppermost surface of the dielectric layer;
removing a portion of the etch stop layer and the barrier layer between the spacers to form an opening, wherein the opening exposes an upper surface of a channel layer; and
forming a T-shaped gate structure above the uppermost surface of the channel layer in the opening, wherein the T-shaped gate structure comprises:
a narrow bottom portion extending from the uppermost surface of the spacers to no further than a lowermost surface of the barrier layer, the narrow bottom portion having sidewalls that are substantially flush with sidewalls of the gate spacers, and
a wide upper portion that extends from the uppermost surface of the spacers to the uppermost surface of the dielectric layer, the wide upper portion having a lowermost surface only in contact with the narrow bottom portion and the uppermost surface of the gate spacers.

### Claim 6 (depends on 5)

The method of claim 5, further comprising forming a delta-doped region above a bottom surface of the barrier layer by doping the region with an element from Group IV, II, or VI of the Periodic Table of Elements.

### Claim 7 (depends on 5)

The method of claim 5, wherein the upper portion of the T-shaped gate structure is laterally wider, by the combined width of the gate spacers, than the bottom portion of the T-shaped gate structure.

### Claim 8 (depends on 5)

The method of claim 5, wherein the forming the T-shaped gate structure in the opening comprises forming a gate dielectric layer and a gate conductor thereon.

### Claim 9 (depends on 5)

The method of claim 5, further comprising forming an undoped region between the bottom portion of the T-shaped gate structure and the channel layer.