# US 9,041,059 B2 · Semiconductor structure for antenna switching circuit

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- Number: US 9,041,059 B2
- Document ID: US9041059B2
- Status: Granted
- Kind: B2
- Application number: 13/886,778
- Filed: 2013-05-03
- Published: 2014-01-30
- Granted: 2015-05-26
- Earliest claimed: 2012-07-27
- Assignees: Maxtek Technology Co., Ltd.
- Applicants: Maxtek Technology Co., Ltd.
- Inventors: Ke-Kung Liao; Tung-Sheng Chang; Chun-Yen Ku; Shih-Yu Chen
- Web page: https://patentgrep.com/patent/US9041059B2

## CPC

- H10D 8/60: Schottky-barrier diodes
- H10D 8/051: {of Schottky diodes}
- H10D 30/87: FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] {(FETs having Schottky contact on top of heterojunction gate H10D30/801)}
- H10D 64/111: {Field plates}
- H10D 64/112: {comprising multiple field plate segments}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A manufacturing method for antenna switching circuit includes the following steps of: providing a GaAs wafer, which includes a capping layer; disposing an isolation layer to the GaAs wafer for forming a device area; and disposing a gate metal on the capping layer within the device area, wherein an interface between the gate metal and the capping layer forms a Schottky contact, and the Schottky contact is parallel connected with an impedance. The present invention also discloses a semiconductor structure for antenna switching circuit.

## Claims

### Claim 1

A semiconductor structure for an antenna switching circuit, comprising:
a buffer layer;
a channel layer disposed on the channel layer;
a space layer disposed on the channel layer;
a donor layer disposed on the space layer;
a capping layer disposed on the donor layer;
an isolation layer disposed on the buffer layer, and adjoining the channel layer, the space layer, the donor layer and the capping layer to form a device area;
a gate metal disposed to the capping layer within the device area, wherein the gate metal and the capping layer have an interface;
a first ohmic layer disposed on the capping layer and contacted to the gate metal; and
a first metal layer disposed on the first ohmic layer and the gate metal.

### Claim 2 (depends on 1)

The semiconductor structure as recited in claim 1, wherein the material of the gate metal includes Au, Pt, Al, Ti, or Ni.

### Claim 3 (depends on 1)

The semiconductor structure as recited in claim 1, wherein the interface of the gate metal and the donor layer is configured with a Schottky contact and an impedance connecting with the Schottky contact in parallel.

### Claim 4 (depends on 1)

The semiconductor structure as recited in claim 1, further comprising:
a second ohmic layer disposed on the capping layer;
a second metal layer disposed on the second ohmic layer.

### Claim 5 (depends on 4)

The semiconductor structure as recited in claim 4, wherein the first ohmic layer adjoins the gate metal.