# US 9,041,058 B2 · Metal oxide semiconductor having epitaxial source drain regions and method of manufacturing same using dummy gate process

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- Number: US 9,041,058 B2
- Document ID: US9041058B2
- Status: Granted
- Kind: B2
- Application number: 13/615,799
- Filed: 2012-09-14
- Published: 2013-01-10
- Granted: 2015-05-26
- Earliest claimed: 2006-12-11
- Assignees: Sony Corporation
- Applicants: Yasushi Tateshita
- Inventors: Yasushi Tateshita
- Web page: https://patentgrep.com/patent/US9041058B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/605: {having significant overlap between the lightly-doped extensions and the gate electrode}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 30/794: {comprising conductive materials, e.g. silicided source, drain or gate electrodes}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/311: {Gate electrodes for field-effect devices}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/668: {the layer being a silicide, e.g. TiSi2}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a transistor by which sufficient stress can be applied to a channel region within allowable ranges of concentrations of Ge and C in a mixed crystal layer. A semiconductor device is also provided.

## Claims

### Claim 1

A semiconductor device comprising:
a silicon substrate;
a gate electrode over the silicon substrate;
a gate insulating film composed of a metal oxide, a metal silicate, a metal oxynitride, or a nitrided metal silicate each including a metal selected from the group consisting of hafnium, lanthanum, aluminum, zirconium, and tantalum, the gate insulating film being only between the gate electrode and the silicon substrate;
as viewed in cross section, a sidewall film on both of oppositely facing sides of the gate electrode;
as viewed in the cross section, an offset spacer between the sidewall film and the gate electrode;
a mixed crystal layer in a recess region of a surface of the silicon substrate on both sides of the sidewall film and composed of silicon and an atom having a lattice constant different from a lattice constant of silicon;
as viewed in the cross section, a shallow-junction extension region on the silicon substrate and extending from the mixed crystal layer to a channel region underneath the gate electrode; and
an insulating film covering the sidewall film and the silicon substrate but not above the gate electrode.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the gate insulating film includes a silicon oxide film between one of the metal silicate, the metal oxynitride, and the nitrided metal silicate and the silicon substrate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the gate electrode is made of A1 or Cu.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the insulating film has a polished surface at the same level as top surface of the gate electrode.

### Claim 5 (depends on 1)

A semiconductor device according to claim 1, wherein the side wall film is partially in contact with the mixed crystal layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the sidewall film comprises an offset spacer layer between the gate electrode and a sidewall layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising a second insulating film on the gate electrode and on the insulating film covering the sidewall film and the silicon substrate.

### Claim 8

A semiconductor device comprising:
a silicon substrate;
a gate electrode over the silicon substrate;
a gate insulating film composed of a metal oxide, a metal silicate, a metal oxynitride, or a nitride metal silicate each including a metal selected from the group consisting of hafnium, lanthanum, aluminum, zirconium, and tantalum, the gate insulating film being only between the gate electrode and the silicon substrate;
as viewed in cross section, a sidewall film at both oppositely facing sides of the gate electrode;
as viewed in the cross section, an offset spacer between the sidewall film and the gate electrode;
a mixed crystal layer in a recess region in a surface of the silicon substrate on both sides of the sidewall film and composed of silicon and an atom having a lattice constant different from a lattice constant of silicon;
an insulating film covering the sidewall film and the silicon substrate but not above the gate electrode; and
a work function control metal between the gate electrode and the gate insulating film.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the work function control metal is made if TiN or TiAIN.

### Claim 10

A semiconductor device comprising:
a silicon substrate;
a gate electrode over the silicon substrate;
a gate insulating film composed of a metal oxide, a metal silicate, a metal oxynitride, or a nitrided metal silicate each including a metal selected from the group consisting of hafnium, lanthanum, aluminum, zirconium, and tantalum, the gate insulating film only between the gate electrode and the silicon substrate;
as viewed in cross section, a sidewall film at both oppositely facing sides of the gate electrode;
as viewed in the cross section, an offset spacer between the sidewall film and the gate electrode;
a mixed crystal layer in a recess region in a surface of the silicon substrate on both sides of the sidewall film and composed of silicon and an atom having a lattice constant different from a lattice constant of silicon:
an insulating film covering the sidewall film and the silicon substrate but not above the gate electrode; and
an adhesion layer between the gate electrode and the gate insulating film.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the adhesion layer is made of Ti or Ta.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, further comprising a second insulating film on the gate electrode and on the insulating film covering the sidewall film and the silicon substrate.