# US 9,041,057 B2 · Field effect transistor device with shaped conduction channel

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- Number: US 9,041,057 B2
- Document ID: US9041057B2
- Status: Granted
- Kind: B2
- Application number: 13/551,164
- Filed: 2012-07-17
- Published: 2012-11-08
- Granted: 2015-05-26
- Earliest claimed: 2010-08-23
- Assignees: International Business Machines Corporation
- Applicants: Dechao Guo; Shu-Jen Han; Chung-Hsun Lin
- Inventors: Dechao Guo; Shu-Jen Han; Chung-Hsun Lin
- Web page: https://patentgrep.com/patent/US9041057B2

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/027: {by etching at gate locations}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.

## Claims

### Claim 1

A field effect transistor device comprising:
a substrate;
a silicon germanium (SiGe) layer disposed on the substrate;
a gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer;
a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity;
ion doped regions disposed in an upper surface of the SiGe layer;
a silicon layer disposed on the ion doped regions of the SiGe layer;
spacers disposed on the ion doped regions of the SiGe layer, the spacers having an outside surface abutting the silicon layer, the spacers further defining the cavity, and the gate dielectric layer lining an entire inside surface of the spacers;
a source region; and
a drain region, wherein the source and drain regions comprise both the silicon layer and the ion doped regions such that a channel length, L, is defined by a distance L=(2*L1+L2), wherein L1 is a distance between the ion doped regions and the substrate, and L2 is a distance comprising a width of the metallic gate material and the gate dielectric layer.

### Claim 2 (depends on 1)

The device of claim 1, wherein the SiGe layer includes a graduated proportion of germanium (Ge) to silicon (Si) such that a proportion of Ge to Si in a region of the SiGe layer adjacent to the substrate is lower than a proportion of Ge to Si in a region of the SiGe layer proximate to the source and drain regions.

### Claim 3 (depends on 1)

The device of claim 1, wherein the silicon layer is an epitaxially grown doped silicon material.

### Claim 4 (depends on 1)

The device of claim 1, wherein the substrate includes a silicon material.

### Claim 5

A field effect transistor device comprising:
a substrate;
a silicon germanium (SiGe) layer disposed on the substrate;
a gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a bottom surface of the gate dielectric layer being coplanar with a top surface of the substrate;
a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity;
ion doped regions disposed in an upper surface of the SiGe layer;
a silicon layer disposed on the ion doped regions of the SiGe layer;
spacers disposed on the ion doped regions of the SiGe layer, the spacers having an outside surface abutting the silicon layer, the spacers further defining the cavity, and the gate dielectric layer lining an entire inside surface of the spacers;
a source region; and
a drain region, wherein the source and drain regions comprise both the silicon layer and the ion doped regions such that a channel length, L, is defined by a distance L=(2*L1+L2), wherein L1 is a distance between the ion doped regions and the substrate, and L2 is a distance comprising a width of the metallic gate material and the gate dielectric layer; and
wherein the SiGe layer includes a graduated proportion of germanium (Ge) to silicon (Si) such that a proportion of Ge to Si in a region of the SiGe layer adjacent to the substrate is lower than a proportion of Ge to Si in a region of the SiGe layer proximate to the source and drain regions.

### Claim 6 (depends on 5)

The device of claim 5, wherein the silicon material is an epitaxially grown doped silicon material.