# US 9,041,056 B2 · Semiconductor device and method of manufacturing same

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- Number: US 9,041,056 B2
- Document ID: US9041056B2
- Status: Granted
- Kind: B2
- Application number: 13/346,906
- Filed: 2012-01-10
- Published: 2012-07-12
- Granted: 2015-05-26
- Earliest claimed: 2011-01-12
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Toshitaka Miyata; Kanna Adachi; Shigeru Kawanaka
- Inventors: Toshitaka Miyata; Kanna Adachi; Shigeru Kawanaka
- Web page: https://patentgrep.com/patent/US9041056B2

## CPC

- H10D 30/00: Field-effect transistors [FET] (insulated-gate bipolar transistors H10D12/00)
- H10D 30/605: {having significant overlap between the lightly-doped extensions and the gate electrode}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/165: {Tunnel injectors}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/8325: {Silicon carbide}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

According to one embodiment, a semiconductor device including: a substrate; a gate electrode formed above the substrate; a gate insulating film formed under the gate electrode; a channel layer formed under the gate insulating film by using a channel layer material; a source region and a drain region formed in the substrate so as to interpose the channel layer therebetween in a channel direction; and a source extension layer formed in the substrate between the channel layer and the source region so as to overlap a source-side end portion of the channel layer. The source extension layer forms a heterointerface with the channel layer. The heterointerface is a tunnel channel for carries.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
a gate electrode formed above the substrate;
a gate insulating film formed under the gate electrode;
a channel layer formed under the gate insulating film by using a channel layer material, the channel layer material being a material different from that of the substrate;
a source region and a drain region formed in the substrate so as to interpose the channel layer therebetween in a channel direction; and
a source extension layer formed in the substrate between the channel layer and the source region so as to be abutted on a source-side end portion of the channel layer, the source extension layer forming a heterointerface with the channel layer, and the heterointerface being a tunnel channel for carries and extending in a first direction parallel to a surface of the substrate, the surface of the substrate being opposed to a lower surface of the gate insulating film via the channel layer,
wherein the material of the substrate and the channel layer material respectively have first and second band gaps to cause the carriers to flow in a second direction perpendicular to the surface of the substrate through the heterointerface.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second band gap is wider than the first band gap.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the source extension layer is abutted on portions of a side surface and a lower surface of the channel layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a channel-direction overlap length of the source extension layer with respect to the channel layer is in a range of 5% to 10% of a channel-direction length of the channel layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the substrate is made of silicon, and the channel layer material is made of a silicon carbide.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the channel layer material is made of at least one of 3C—SiC, 4H—SiC, and 6H—SiC.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising: a drain extension layer formed in the substrate between the channel layer and the drain region so as to be abutted on a drain-side end portion of the channel layer, the drain extension layer forming a heterointerface with the channel layer, the heterointerface being a tunnel channel for the carries and extending in the first direction.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the drain extension layer is abutted on portions of a side surface and a lower surface of the channel layer.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein a channel-direction overlap length of the drain extension layer with respect to the channel layer is in a range of 5% to 10% of a channel-direction length of the channel layer.