# US 9,041,054 B2 · High holding voltage electrostatic discharge protection device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,041,054 B2 - Document ID: US9041054B2 - Status: Granted - Kind: B2 - Application number: 14/181,141 - Filed: 2014-02-14 - Published: 2014-06-12 - Granted: 2015-05-26 - Earliest claimed: 2010-02-22 - Assignees: Sofics BVBA - Applicants: Sofics BVBA - Inventors: Sven Van Wijmeersch; Olivier Marichal - Web page: https://patentgrep.com/patent/US9041054B2 ## CPC - H10D 8/80: PNPN diodes, e.g. Shockley diodes or break-over diodes - H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage. ## Claims ### Claim 1 An electrostatic discharge (ESD) protection circuit comprising: a first well, wherein the first well is lowly-doped and has an N-type conductivity; a second well, wherein the second well is lowly-doped and has a P-type conductivity; a first region formed within the first well, wherein the first region has the P-type conductivity and functions as an anode of the ESD protection circuit; a second region formed within the second well, wherein the second region has the N-type conductivity and functions as a cathode of the ESD protection circuit; a third region formed within the first well, wherein the third region is highly-doped and has the N-type conductivity; a fourth region formed within the second well, wherein the fourth region is highly-doped and has the P-type conductivity; a fifth region formed within the second well between the first well and the second region, wherein the fifth region is highly-doped and has the P-type conductivity; and a sixth region formed within the second well, wherein the sixth region is highly-doped, has the N-type conductivity, and is electrically coupled to the fifth region; wherein a first PNP transistor is formed by an emitter including the first region, a base including the first well, and a collector including the second well; a first NPN transistor is formed by an emitter including the second region, a base including the second well, and a collector including the first well; and a second NPN transistor is formed by an emitter including the second region, a base including the second well, and a collector including the sixth region. ### Claim 2 (depends on 1) The ESD protection circuit of claim 1, wherein the sixth region is formed between the second region and the fourth region. ### Claim 3 (depends on 1) The ESD protection circuit of claim 1, wherein the fourth region is formed between the second region and the sixth region. ### Claim 4 (depends on 1) The ESD protection circuit of claim 1, wherein the first region is a lowly-doped region, and further wherein one or more additional regions are nested within the first region. ### Claim 5 (depends on 4) The ESD protection circuit of claim 4, wherein the one or more additional regions comprises a region of the N-type conductivity. ### Claim 6 (depends on 1) The ESD protection circuit of claim 1, wherein the second region is a lowly-doped region, and further wherein one or more additional regions are nested within the second region. ### Claim 7 (depends on 6) The ESD protection circuit of claim 6, wherein the one or more additional regions comprises a region of the P-type conductivity. ### Claim 8 (depends on 1) The ESD protection circuit of claim 1, further comprising a diode in reverse conduction mode coupled from the fifth region to the second region. ### Claim 9 (depends on 1) The ESD protection circuit of claim 1, further comprising a seventh region formed partially within both the first well and the second well such that the seventh region spans a junction between the first well and the second well. ### Claim 10 (depends on 1) The ESD protection circuit of claim 1, further comprising: a seventh region formed within the first well, wherein the seventh region is highly-doped, has the P-type conductivity, and is coupled to the fifth region; wherein a second PNP transistor is formed by an emitter including the first region, a base including the first well, and a collector including the seventh region. ### Claim 11 (depends on 10) The ESD protection circuit of claim 10, wherein the seventh region is formed between the third region and the first region. ### Claim 12 (depends on 10) The ESD protection circuit of claim 10, further comprising: an eighth region, wherein the eighth region is lowly-doped and has the P-type conductivity; wherein the seventh region is formed within the eighth region, and wherein the eighth region is formed within the first well. ### Claim 13 (depends on 1) The ESD protection circuit of claim 1, further comprising: a seventh region formed within the first well between the first region and the second well, wherein the seventh region is highly-doped and has the N-type conductivity; and an eighth region formed within the first well, wherein the eighth region is highly-doped, has the P-type conductivity, and is electrically coupled to the seventh region. ### Claim 14 (depends on 1) The ESD protection circuit of claim 1, further comprising: a seventh region, wherein the seventh region is lowly-doped and has the N-type conductivity; wherein the sixth region is formed within the seventh region, and wherein the seventh region is formed within the second well. ### Claim 15 (depends on 1) The ESD protection circuit of claim 1, further comprising: a trigger circuit to turn on the ESD protection circuit during an ESD event, wherein the trigger circuit is electrically coupled between any two of: the first region, the second region, the third region, the fourth region, the fifth region, and the sixth region. ### Claim 16 (depends on 1) The ESD protection circuit of claim 1, wherein the first region is high-doped and the second region is highly-doped. ### Claim 17 An electrostatic discharge (ESD) protection circuit comprising: a first well, wherein the first well is lowly-doped and has an N-type conductivity; a second well, wherein the second well is lowly-doped and has a P-type conductivity; a first region formed within the first well, wherein the first region has the P-type conductivity and functions as an anode of the ESD protection circuit; a second region formed within the second well, wherein the second region has the N-type conductivity and functions as a cathode of the ESD protection circuit; a third region formed within the first well, wherein the third region is highly-doped and has the N-type conductivity; a fourth region formed within the second well, wherein the fourth region is highly-doped and has the P-type conductivity; a fifth region formed within the first well between the first region and the second well, wherein the fifth region is highly-doped and has the N-type conductivity; and a sixth region formed within the first well, wherein the sixth region is highly-doped, has the P-type conductivity; and is electrically coupled to the fifth region; wherein a first PNP transistor is formed by an emitter including the first region, a base including the first well, and a collector including the second well; a first NPN transistor is formed by an emitter including the second region, a base including the second well, and a collector including the first well; and a second PNP transistor is formed by an emitter including the first region, a base including the first well, and a collector including the sixth region. ### Claim 18 (depends on 17) The ESD protection circuit of claim 17, wherein the sixth region is formed between the third region and the first region. ### Claim 19 (depends on 17) The ESD protection circuit of claim 17, wherein the third region is formed between the sixth region and the first region. ### Claim 20 (depends on 17) The ESD protection circuit of claim 17, wherein the first region is a lowly-doped region, and further wherein one or more additional regions are nested within the first region. ### Claim 21 (depends on 20) The ESD protection circuit of claim 20, wherein the one or more additional regions comprises a region of the N-type conductivity. ### Claim 22 (depends on 17) The ESD protection circuit of claim 17, wherein the second region is a lowly-doped region, and further wherein one or more additional regions are nested within the second region. ### Claim 23 (depends on 22) The ESD protection circuit of claim 22, wherein the one or more additional regions comprises a region of the P-type conductivity. ### Claim 24 (depends on 17) The ESD protection circuit of claim 17, further comprising a diode in reverse conduction mode coupled from the first region to the fifth region. ### Claim 25 (depends on 17) The ESD protection circuit of claim 17, further comprising a seventh region formed partially within both the first well and the second well such that the seventh region spans a junction between the first well and the second well. ### Claim 26 (depends on 17) The ESD protection circuit of claim 17, further comprising: a seventh region formed within the second well, wherein the seventh region is highly-doped, has the N-type conductivity, and is coupled to the fifth region; wherein a second NPN transistor is formed by an emitter including the second region, a base including the second well, and a collector including the seventh region. ### Claim 27 (depends on 26) The ESD protection circuit of claim 26, wherein the seventh region is formed between the second region and the fourth region. ### Claim 28 (depends on 26) The ESD protection circuit of claim 26, further comprising: an eighth region, wherein the eighth region is lowly-doped and has the N-type conductivity; wherein the seventh region is formed within the eighth region, and wherein the eighth region is formed within the second well. ### Claim 29 (depends on 17) The ESD protection circuit of claim 17, further comprising: a trigger circuit to turn on the ESD protection circuit during an ESD event, wherein the trigger circuit is electrically coupled between any two of: the first region, the second region, the third region, the fourth region, the fifth region, and the sixth region. ### Claim 30 (depends on 17) The ESD protection circuit of claim 17, wherein the first region is high-doped and the second region is highly-doped.