# US 9,041,052 B2 · Semiconductor device, semiconductor unit, and power semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,041,052 B2 - Document ID: US9041052B2 - Status: Granted - Kind: B2 - Application number: 13/052,025 - Filed: 2011-03-18 - Published: 2011-11-24 - Granted: 2015-05-26 - Earliest claimed: 2010-05-21 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Satoshi Teramae - Inventors: Satoshi Teramae - Web page: https://patentgrep.com/patent/US9041052B2 ## CPC - H10W 90/00: Package configurations - H05K 1/0209: {External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings} - H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates} - H10W 70/65: Shapes or dispositions of interconnections - H05K 3/0061: {onto a metallic substrate, e.g. a heat sink (heat sinks for electric apparatus H05K7/20)} - H05K 3/222: {Completing of printed circuits by adding non-printed jumper connections (printed jumper connections H05K3/4685)} - H05K 2201/09663: Divided layout, i.e. conductors divided in two or more parts - H05K 2201/0969: Apertured conductors - H05K 2201/1028: Thin metal strips as connectors or conductors - H05K 2201/10287: Metal wires as connectors or conductors - H10W 72/07336: {Soldering or alloying} - H10W 72/07352: {changes in structures or sizes} - H10W 72/321: {Structures or relative sizes of die-attach connectors} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/5524: {comprising aluminium [Al]} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 76/12: characterised by their shape - H10W 76/136: having other interconnections perpendicular to the conductive base - H10W 76/47: Solid or gel fillings - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A semiconductor device includes: an insulating substrate; a first electrode pattern and a second electrode pattern provided apart from each other on a major surface of the insulating substrate; a semiconductor element connected to the first electrode pattern; an electrode terminal connected to the second electrode pattern; and a connection wiring. The connection wiring electrically connects the first electrode pattern and the second electrode pattern with each other and has a thermal resistance larger than that of the first electrode pattern. ## Claims ### Claim 1 A semiconductor device, comprising: an insulating substrate; a first electrode pattern and a second electrode pattern provided apart from each other on a major surface of the insulating substrate; a first semiconductor element connected to the first electrode pattern; a second semiconductor element connected to the first electrode pattern; a third semiconductor element connected to the second electrode pattern; a fourth semiconductor element connected to the second electrode pattern; an electrode terminal connected to the second electrode pattern; a connection wiring electrically connecting the first electrode pattern and the second electrode pattern to each other and having a thermal resistance larger than that of the first electrode pattern; a first connection member connecting the first electrode pattern and the first semiconductor element to each other; and a second connection member connecting the second electrode pattern and the electrode terminal to each other and having a melting point lower than that of the first connection member, wherein the insulating substrate includes a first insulating substrate on which the first electrode pattern is provided and a second insulating substrate on which the second electrode pattern is provided, the second insulating substrate being provided apart from the first insulating substrate, the first semiconductor element and the second semiconductor element each comprise a switching element respectively configured to be in a conducting state during different operating periods, the third semiconductor element and the fourth semiconductor element each comprise a switching element respectively configured to be in a conducting state during different operating periods, the first semiconductor element and the third semiconductor element each comprise a switching element respectively configured to be in a conducting state during operating periods which overlap with each other at least in a part thereof, and the second semiconductor element and the fourth semiconductor element each comprise a switching element respectively configured to be in a conducting state during operating periods which overlap with each other at least in a part thereof. ### Claim 2 (depends on 1) The device according to claim 1, wherein a melting point of the first connection member is higher than an operating temperature of the first semiconductor element. ### Claim 3 (depends on 1) The device according to claim 1, wherein an area of a cross section in the connection wiring along a first direction is smaller than an area of a cross section in the first electrode pattern along the first direction, the first direction being a direction perpendicular to a direction extending from the first electrode pattern towards the second electrode pattern. ### Claim 4 (depends on 3) The device according to claim 3, wherein the connection wiring is provided with a hole. ### Claim 5 (depends on 3) The device according to claim 3, wherein a width of the connection wiring along the first direction is narrower than a width of the first electrode pattern along the first direction. ### Claim 6 (depends on 1) The device according to claim 1, wherein a material of the connection wiring is different from a material of the first electrode pattern. ### Claim 7 (depends on 1) The device according to claim 1, wherein a material of the connection wiring is the same as a material of the first electrode pattern. ### Claim 8 (depends on 1) The device according to claim 1, comprising a plurality of semiconductor elements, wherein a condition, L>2D, is satisfied, where L is a spacing width between the plurality of semiconductor elements along the major surface and D is a distance from a surface of each semiconductor element that is facing the major surface to a surface of the insulating substrate that is opposite the major surface. ### Claim 9 (depends on 1) The device according to claim 1, wherein a bonding wire is used as the connection wiring. ### Claim 10 (depends on 1) The device according to claim 1, wherein a bus bar is used as the connection wiring. ### Claim 11 (depends on 1) The device according to claim 1, wherein a ceramic substrate is used as the insulating substrate. ### Claim 12 (depends on 1) The device according to claim 1, wherein copper is used as the first electrode pattern and the second electrode pattern, and aluminum is used as the connection wiring. ### Claim 13 (depends on 1) The semiconductor device of claim 1, wherein the first through fourth semiconductor elements are disposed in an array such that the first and third semiconductor elements are adjacent to each other in a first direction, the second and fourth semiconductor elements are adjacent to each other in the first direction, the first and second semiconductor are adjacent to each other in a second direction crossing the first direction, and the third and fourth semiconductor elements are adjacent to each other in the second direction. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the first and third semiconductor elements are insulated gate bipolar transistors and the second and fourth semiconductor elements are fast recovery diodes. ### Claim 15 (depends on 1) The semiconductor device of claim 1, further comprising: a control unit configured to control the conducting state of the first and third semiconductor elements to each be in an ON state during respective operating periods which at least partly overlap with each other, wherein the second and fourth semiconductor elements are each diodes reverse-connected with respect to an ON state conductance path of the first and third semiconductor elements, respectively. ### Claim 16 A semiconductor unit, comprising: a semiconductor device including: an insulating substrate; a first electrode pattern and a second electrode pattern provided apart from each other on a major surface of the insulating substrate; a first semiconductor element connected to the first electrode pattern; a second semiconductor element connected to the first electrode pattern; a third semiconductor element connected to the second electrode pattern; a fourth semiconductor element connected to the second electrode pattern; an electrode terminal connected to the second electrode pattern; a connection wiring electrically connecting the first electrode pattern and the second electrode pattern with each other and having a thermal resistance larger than that of the first electrode pattern; a first connection member connecting the first electrode pattern and the first semiconductor element to each other; a second connection member connecting the second electrode pattern and the electrode terminal to each other and having a melting point lower than that of the first connection member; and a package accommodating therein at least the first semiconductor element, the connection wiring, and a part of the electrode terminal, wherein the insulating substrate includes a first insulating substrate on which the first electrode pattern is provided and a second insulating substrate on which the second electrode pattern is provided, the second insulating substrate being provided apart from the first insulating substrate, the first semiconductor element and the second semiconductor element each comprise a switching element respectively configured to be in a conducting state during different operating periods, the third semiconductor element and the fourth semiconductor element each comprise a switching element respectively configured to be in a conducting state during different operating periods, the first semiconductor element and the third semiconductor element each comprise a switching element respectively configured to be in a conducting state during operating periods which overlap with each other at least in a part thereof, and the second semiconductor element and the fourth semiconductor element each comprise a switching element respectively configured to be in a conducting state during operating periods which overlap with each other at least in a part thereof. ### Claim 17 A power semiconductor device, comprising; an insulating substrate; a first electrode pattern and a second electrode pattern provided apart from each other on a major surface of the insulating substrate; a first power semiconductor element connected to the first electrode pattern; a second power semiconductor element connected to the first electrode pattern; a third power semiconductor element connected to the second electrode pattern; a fourth power semiconductor element connected to the second electrode pattern; an electrode terminal connected to the second electrode pattern; a connection wiring electrically connecting the first electrode pattern to the second electrode pattern and having a thermal resistance larger than a thermal resistance of the first electrode pattern; a first connection member connecting the first electrode pattern to the first power semiconductor element; and a second connection member connecting the second electrode pattern to the electrode terminal and having a melting point lower than that of the first connection member, wherein the insulating substrate includes a first insulating substrate on which the first electrode pattern is provided and a second insulating substrate on which the second electrode pattern is provided, the second insulating substrate being provided apart from the first insulating substrate, the first power semiconductor element and the second power semiconductor element each comprise a switching element respectively configured to be in a conducting state during different operating periods, the third power semiconductor element and the fourth power semiconductor element each comprise a switching element respectively configured to be in a conducting state during different operating periods, the first power semiconductor element and the third power semiconductor element each comprise a switching element respectively configured to be in a conducting state during operating periods which overlap with each other at least in a part thereof, and the second power semiconductor element and the fourth power semiconductor element each comprise a switching element respectively configured to be in a conducting state during operating periods which overlap with each other at least in a part thereof. ### Claim 18 (depends on 17) The power semiconductor device of claim 17, wherein the first connection member also connects the first electrode pattern to the second power semiconductor element. ### Claim 19 (depends on 17) The power semiconductor device of claim 17, wherein the first power semiconductor element includes an insulated gate bipolar transistor.