# US 9,041,051 B2 · Semiconductor device

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- Number: US 9,041,051 B2
- Document ID: US9041051B2
- Status: Granted
- Kind: B2
- Application number: 14/111,168
- Filed: 2011-07-05
- Published: 2014-07-17
- Granted: 2015-05-26
- Earliest claimed: 2011-07-05
- Assignees: Mitsubishi Electric Corporation
- Applicants: Ze Chen; Katsumi Nakamura
- Inventors: Ze Chen; Katsumi Nakamura
- Web page: https://patentgrep.com/patent/US9041051B2

## CPC

- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 12/411: {Insulated-gate bipolar transistors [IGBT]}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/137: {Collector regions of BJTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/231: {Emitter or collector electrodes for bipolar transistors}
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An insulated gate bipolar transistor having a gate electrode (7) and an emitter electrode (9) is provided in a transistor region. A termination region is arranged around the transistor region. A first N type buffer layer (18) is provided below an N type drift layer (1) in the transistor region. A P type collector layer (19) is provided below the first N type buffer layer (18). A second N type buffer layer (20) is provided below the N type drift layer (1) in the termination region. A collector electrode (21) is directly connected to the P type collector layer (19) and the second N type buffer layer (20). An impurity concentration of the second N type buffer layer (20) decreases as a distance from the collector electrode (21) decreases. The second N type buffer layer (20) does not form any ohmic contact with the collector electrode (21).

## Claims

### Claim 1

A semiconductor device comprising:
a transistor region in which an insulated gate bipolar transistor having a gate electrode and an emitter electrode is provided; and
a termination region arranged around the transistor region,
wherein a first N type buffer layer is provided below an N type drift layer in the transistor region,
a P type collector layer is provided below the first N type buffer layer,
a second N type buffer layer is provided below the N type drift layer in the termination region,
a collector electrode is directly connected to the P type collector layer and the second N type buffer layer,
an impurity concentration of the second N type buffer layer decreases as a distance from the collector electrode decreases, and
the second N type buffer layer does not form any ohmic contact with the collector electrode.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising a PN junction region arranged between the transistor region and the termination region,
wherein a first P type layer is provided on the N type drift layer in the PN junction region,
a gate wiring is provided on the first P type layer via an insulating film, and
the gate wiring is connected to the gate electrode.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein an N type layer is provided on the first P type layer, and
the N type layer is connected to the emitter electrode.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein a second P type layer is provided between the N type layer and the emitter electrode.