# US 9,041,049 B2 · Power JFET

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- Number: US 9,041,049 B2
- Document ID: US9041049B2
- Status: Granted
- Kind: B2
- Application number: 13/970,586
- Filed: 2013-08-19
- Published: 2013-12-19
- Granted: 2015-05-26
- Earliest claimed: 2011-02-01
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Koichi Arai; Yasuaki Kagotoshi; Nobuo Machida; Natsuki Yokoyama; Haruka Shimizu
- Web page: https://patentgrep.com/patent/US9041049B2

## CPC

- H10D 62/60: Impurity distributions or concentrations
- H10D 30/0515: {of vertical FETs having PN homojunction gates}
- H10D 30/831: {Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202)}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/8325: {Silicon carbide}
- H10D 64/411: {for FETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

## Claims

### Claim 1

A power JFET, comprising:
a silicon-carbide-based semiconductor substrate having a first main surface having a first conductivity type, the silicon-carbide-based semiconductor substrate including:
a first silicon-carbide-based semiconductor epitaxial layer having the same conductivity type as the first conductivity type and a concentration lower than that of the silicon-carbide-based semiconductor substrate;
a second silicon-carbide-based semiconductor epitaxial layer having the same conductivity type as the first conductivity type and a concentration lower than that of the semiconductor substrate and provided in a surface of the first silicon-carbide-based semiconductor epitaxial layer corresponding to the first main surface of the semiconductor wafer;
a plurality of first gate impurity regions doped with an impurity having a second conductivity type and provided in the first silicon-carbide-based semiconductor epitaxial layer; and
a plurality of second gate impurity regions doped with an impurity having the second conductivity type and provided in the second silicon-carbide-based semiconductor epitaxial layer,
wherein the first gate impurity regions and the second gate impurity regions are continuously aligned.

### Claim 2 (depends on 1)

A power JFET according to claim 1,
wherein the first gate impurity regions are formed by doping the surface of the first silicon-carbide-based semiconductor epitaxial layer with the impurity having the second conductivity type by ion implantation and performing first activation annealing thereon, and
wherein the second gate impurity regions are formed by doping a surface of the second silicon-carbide-based semiconductor epitaxial layer with the impurity having the second conductivity type by ion implantation and performing second activation annealing thereon.

### Claim 3 (depends on 2)

A power JFET according to claim 2,
wherein the first activation annealing and the second activation annealing are each performed in a state where the first main surface of the semiconductor wafer is covered with a carbon-based film.