# US 9,041,009 B2 · Method and structure for forming high-K/metal gate extremely thin semiconductor on insulator device

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- Number: US 9,041,009 B2
- Document ID: US9041009B2
- Status: Granted
- Kind: B2
- Application number: 13/770,534
- Filed: 2013-02-19
- Published: 2013-06-20
- Granted: 2015-05-26
- Earliest claimed: 2010-08-19
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Bruce B. Doris; Kangguo Cheng; Ali Khakifirooz; Pranita Kerber
- Web page: https://patentgrep.com/patent/US9041009B2

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

## Claims

### Claim 1

A semiconductor device comprising:
a gate structure present on a substrate, the gate structure comprising a gate dielectric and a gate conductor, said gate conductor having an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region, and wherein a topmost surface of said gate dielectric is coplanar with a topmost surface of said gate conductor;
a spacer adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region and wherein said spacer is entirely spaced apart from said gate conductor by a portion of said gate dielectric; and
a raised source region and a raised drain region present adjacent to the spacer, wherein the raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacer and have a topmost surface that is vertically offset from a topmost surface of the substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the substrate is composed of a semiconductor material that is selected from the group consisting of Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs, InP, and combinations thereof.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the substrate is comprised of a semiconductor layer having a thickness of less than 10 nm that is present on a dielectric layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the gate dielectric comprises a high-k gate dielectric and the gate conductor comprises a metal.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the high-k gate dielectric is a dielectric selected from the group consisting of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and combinations thereof.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein the metal from the gate conductor is selected from the group consisting of W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, Au, Ru, Ir, Rh, Re and combinations thereof.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the undercut region has a length ranging from 1 nm to 20 nm, as measured from a sidewall of the second portion of the gate conductor.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the spacer is an oxide, nitride or oxynitride material.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the extending portion of the spacer has a width ranging from 5 nm to 50 nm.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein extending portion of the spacer has a width that ranges from 10 nm to 40 nm.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the extending portion of the spacer has a width that ranges from 15 nm to 30 nm.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein another surface of the gate dielectric is in direct physical contact with a portion of the topmost surface of the substrate.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the topmost surface of the raised source region and the raised drain region is vertically offset and located below an upper surface of the extending portion of the spacer.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein the spacer is a unitary structure.

### Claim 15 (depends on 1)

The semiconductor device of claim 1, wherein the substrate is a semiconductor on insulator (SOI) substrate, and the semiconductor device further includes extension regions having a depth that extends an entire depth of a semiconductor on insulator (SOI) layer of the SOI substrate.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the extension regions have a depth of less than 10 nm.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the extension regions have a depth ranging from 3 nm to 8 nm.