# US 9,041,008 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 9,041,008 B2
- Document ID: US9041008B2
- Status: Granted
- Kind: B2
- Application number: 13/411,789
- Filed: 2012-03-05
- Published: 2012-09-13
- Granted: 2015-05-26
- Earliest claimed: 2011-03-10
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Yukio Nakabayashi; Takashi Shinohe; Atsuko Yamashita
- Inventors: Yukio Nakabayashi; Takashi Shinohe; Atsuko Yamashita
- Web page: https://patentgrep.com/patent/US9041008B2

## CPC

- H10D 12/031: {of IGBTs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/8325: {Silicon carbide}
- H10P 30/2042: {into crystalline silicon carbide}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device of an embodiment includes a first conductive type silicon carbide substrate having first and second main surfaces, a first conductive type silicon carbide layer formed on the first main surface, a second conductive type first silicon carbide region formed in the silicon carbide layer, and a first conductive type second silicon carbide region formed in the first silicon carbide region. The device includes a trench penetrating through the first and second silicon carbide regions, and a second conductive type third silicon carbide region formed on a bottom and a side surface of the trench. The third silicon carbide region is in contact with the first silicon carbide region, and is formed between the trench and the silicon carbide layer. In addition, the device includes a gate insulating film formed in the trench, a gate electrode, a first electrode, and a second electrode.

## Claims

### Claim 1

A semiconductor device comprising:
a first conductive type silicon carbide substrate having first and second surfaces;
a first conductive type silicon carbide layer provided on the first surface of the silicon carbide substrate;
a second conductive type first silicon carbide region provided on the silicon carbide layer;
a first conductive type second silicon carbide region provided on the first silicon carbide region;
a second conductive type third silicon carbide region provided selectively in the silicon carbide layer, the third silicon carbide region being in contact with the first silicon carbide region;
a gate electrode provided in the second silicon carbide region, the first silicon carbide region, and the third silicon carbide region;
a gate insulating film provided between the gate electrode and the second silicon carbide region, the gate insulating film provided between the gate electrode and the first silicon carbide region, the gate insulating film provided between the gate electrode and the third silicon carbide region;
a first electrode provided on the second silicon carbide region; and
a second electrode provided on the second main surface.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein an impurity concentration of the third silicon carbide region is lower than an impurity concentration of the first silicon carbide region.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein a thickness t of the third silicon carbide region on the side of the gate electrode satisfies Equation 1:
t≦(2∈sφbiNd/qNa(Na+Nd))1/2 Equation 1
(where, φbi=(kT/q)×ln(NdNa/ni2), Nd denotes an impurity concentration of the silicon carbide layer, Na denotes an impurity concentration of the third silicon carbide region, ni denotes intrinsic carrier density, q denotes an elementary charge, T denotes an absolute temperature, k denotes a Boltzmann constant, and ∈s denotes a dielectric constant of silicon carbide).

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the gate insulating film is a silicon oxide film.

### Claim 5

A semiconductor device comprising:
a first conductive type silicon carbide substrate having first and second surfaces;
a first conductive type silicon carbide layer provided on the first surface of the silicon carbide substrate;
a second conductive type first silicon carbide region provided on the silicon carbide layer;
a first conductive type second silicon carbide region provided on the first silicon carbide region;
a gate electrode provided in the second silicon carbide region and the first silicon carbide region;
a gate insulating film provided between the gate electrode and the second silicon carbide region, the gate insulating film provided between the gate electrode and the first silicon carbide region;
a first conductive type third silicon carbide region provided selectively in the first silicon carbide region, the third silicon carbide region being in contact with the silicon carbide layer, the third silicon carbide region provided between the silicon carbide layer and the gate insulating film;
a first electrode provided on the second silicon carbide region; and
a second electrode provided on the second main surface.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein a width w of the gate electrode with the gate insulating film satisfies Equation 2:
w≦2×(2∈sφbiNa/qNd(Na+Nd))1/2 Equation 2
(where, φbi=(kT/q)×ln(NdNa/ni2), Nd denotes an impurity concentration of the third silicon carbide region, Na denotes an impurity concentration of the first silicon carbide region, ni denotes intrinsic carrier density, q denotes an elementary charge, T denotes an absolute temperature, k denotes a Boltzmann constant, and ∈s denotes a dielectric constant of silicon carbide).

### Claim 7 (depends on 5)

The semiconductor device according to claim 5, wherein the gate insulating film is a silicon oxide film.