# US 9,041,007 B2 · Semiconductor device

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- Number: US 9,041,007 B2
- Document ID: US9041007B2
- Status: Granted
- Kind: B2
- Application number: 13/299,882
- Filed: 2011-11-18
- Published: 2012-05-31
- Granted: 2015-05-26
- Earliest claimed: 2010-11-25
- Assignees: Mitsubishi Electric Corporation
- Applicants: Eisuke Suekawa; Yasunori Oritsuki; Yoichiro Tarui
- Inventors: Eisuke Suekawa; Yasunori Oritsuki; Yoichiro Tarui
- Web page: https://patentgrep.com/patent/US9041007B2

## CPC

- H10D 30/665: {having edge termination structures}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/669: {having voltage-sensing or current-sensing structures, e.g. emulator sections or overcurrent sensing cells}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/664: {the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer}
- H10D 84/143: {the built-in components being PN junction diodes}
- H10D 62/8325: {Silicon carbide}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n+-source region formed in an upper portion of an n−-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.

## Claims

### Claim 1

A semiconductor device, comprising:
a main transistor cell with a gate insulating film formed on a silicon carbide semiconductor layer, a gate electrode formed on said gate insulating film, and a source region that is an impurity region formed in an upper portion of said semiconductor layer;
an interlayer insulating film in direct contact with said gate electrode;
a source electrode connected to said source region while extending over said interlayer insulating film;
a gate pad connected to said gate electrode; and
a barrier metal layer interposed between said source electrode and said interlayer insulating film, and between said gate pad and said gate electrode, said barrier metal layer formed both over said source region and under said gate pad, said barrier metal layer contacting a horizontal surface of said interlayer insulating film.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising a current sensing cell, the current sensing cell having a gate electrode shared with said main transistor cell, the current sensing cell having a source electrode including aluminum that is different from that of said main transistor cell,
wherein said barrier metal layer is also interposed between said source electrode of said current sensing cell and said interlayer insulating film.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein said barrier metal layer is a TiN layer having a thickness of 90nm or more.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising a compound layer of said semiconductor layer and metal, the compound layer being formed at part of said source region in contact with said source electrode.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein:
a thickness of the barrier metal layer is greater than or equal to 90nm.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein:
the source electrode includes aluminum;
the gate pad includes aluminum; and
the barrier metal layer prevents diffusion of aluminum.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein:
said barrier metal layer extends continuously from the top portion of said interlayer insulating film to the side portion of said interlayer insulating film.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein:
said barrier metal layer has been patterned together with said source electrode and said gate pad.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a silicide layer in ohmic contact with said source region, said silicide layer disposed between said source region and said source electrode.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein:
said barrier metal layer is disposed between said silicide layer and said source electrode.