# US 9,040,986 B2 · Three dimensional integrated circuit having a resistance measurement structure and method of use > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,040,986 B2 - Document ID: US9040986B2 - Status: Granted - Kind: B2 - Application number: 13/356,243 - Filed: 2012-01-23 - Published: 2013-07-25 - Granted: 2015-05-26 - Earliest claimed: 2012-01-23 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Ching-Fang Chen; Hsiang-Tai Lu; Chih-Hsien Lin - Inventors: Ching-Fang Chen; Hsiang-Tai Lu; Chih-Hsien Lin - Web page: https://patentgrep.com/patent/US9040986B2 ## CPC - G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]} - G01R 31/2886: {Features relating to contacting the IC under test, e.g. probe heads; chucks (G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06)} - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/635: {Through-vias} - H10W 72/251: {Materials} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A three-dimensional integrated circuit (3DIC) including a top chip having at least one active device and an interposer having conductive routing layers and vias. The 3DIC further includes a plurality of conductive connectors configured to electrically connect the top chip and the interposer. The 3DIC further includes a conductive line over at least one of the top chip or the interposer. The conductive line traces a perimeter of top chip or interposer parallel to an outer edge of the top chip or interposer. The conductive line is configured to electrically connect the conductive connectors. The 3DIC further includes at least one testing element over at least one of the top chip or the interposer. The testing element is configured to electrically connect to the plurality of conductive connectors. ## Claims ### Claim 1 A three-dimensional integrated circuit (3DIC) comprising: a top chip, wherein the top chip includes at least one active device; an interposer, wherein the interposer includes conductive routing layers and vias; a plurality of conductive connectors, wherein the plurality of conductive connectors are configured to electrically connect the top chip and the interposer; at least one conductive line over at least one of the top chip or the interposer, wherein the at least one conductive line traces a perimeter of the at least one of the top chip or the interposer substantially parallel to an outer edge of the at least one of the top chip or the interposer, and the at least one conductive line is configured to electrically connect the plurality of conductive connectors; and at least one testing element over at least one of the top chip or the interposer, wherein each of the at least one testing element is configured to electrically connect to the plurality of conductive connectors. ### Claim 2 (depends on 1) The 3DIC of claim 1, wherein the at least one conductive line is over both the top chip and the interposer. ### Claim 3 (depends on 1) The 3DIC of claim 1, wherein the at least one testing element comprises a test circuit over at least one of the top chip or the interposer. ### Claim 4 (depends on 1) The 3DIC of claim 1, wherein the at least one testing element comprises a test circuit over both the top chip and the interposer. ### Claim 5 (depends on 1) The 3DIC of claim 1, wherein the at least one testing element comprises conductive pads, wherein the at least one conductive line, the plurality of conductive connectors and the conductive pads form at least one Kelvin structure. ### Claim 6 (depends on 5) The 3DIC of claim 5, wherein the at least one Kelvin structure comprises a Kelvin structure at each corner of at least one of the top chip or the interposer. ### Claim 7 (depends on 5) The 3DIC of claim 5, wherein the at least one Kelvin structure comprises a Kelvin structure at each corner of both the top chip and the interposer. ### Claim 8 (depends on 1) The 3DIC of claim 1, further comprising a first metal sealing ring over the top chip and a second metal sealing ring over the interposer. ### Claim 9 (depends on 8) The 3DIC of claim 8, wherein the at least one conductive line is at least one of the first metal sealing ring or the second metal sealing ring. ### Claim 10 (depends on 8) The 3DIC of claim 8, wherein the at least one conductive line is separate from the first metal sealing ring and the second metal sealing ring. ### Claim 11 (depends on 10) The 3DIC of claim 10, wherein the at least one conductive line is positioned in an area defined by the first metal sealing ring or the second metal sealing ring. ### Claim 12 (depends on 1) The 3DIC of claim 1, further comprising through substrate vias in the interposer, wherein the through substrate vias are configured to electrically connect to the at least one testing element. ### Claim 13 A three-dimensional integrated circuit (3DIC) comprising: a top chip, wherein the top chip includes at least one active device; an interposer, wherein the interposer includes conductive routing layers and vias; a second chip electrically connected to the top chip, wherein the second chip includes at least one active device; a first plurality of conductive connectors, wherein the first plurality of conductive connectors electrically connected to the top chip; a second plurality of conductive connectors, wherein the second plurality of conductive connectors are electrically connected to the second chip; at least one conductive line over at least one of the top chip, the second chip or the interposer, wherein the at least one conductive line traces a perimeter of the at least one of the top chip, the second chip or the interposer substantially parallel to an outer edge of the at least one of the top chip, the second chip or the interposer, and the at least one conductive line is configured to electrically connect the first plurality of conductive connectors or the second plurality of conductive connectors; and at least one testing element over at least one of the top chip, the second chip or the interposer, wherein each of the at least one testing element is electrically connected to the first plurality of conductive connectors or the second plurality of conductive connectors. ### Claim 14 (depends on 13) The 3DIC of claim 13, wherein a space between adjacent conductive connectors of the first plurality of conductive connectors ranges from about 30 microns (μm) to about 50 μm. ### Claim 15 (depends on 13) The 3DIC of claim 13, wherein the at least one testing element comprises a first testing element over the top chip; and a second testing element over the second chip. ### Claim 16 (depends on 13) The 3DIC of claim 13, further comprising a seal ring in the top chip, wherein the at least one conductive layer is over the top chip, and the seal ring surrounds the at least one conductive layer. ### Claim 17 (depends on 13) The 3DIC of claim 13, wherein the interposer is between the top chip and the second chip, the first plurality of conductive connectors is configured to electrically connect the top chip to the interposer, and the second plurality of conductive connectors is configured to electrically connect the second chip to the interposer. ### Claim 18 (depends on 13) The 3DIC of claim 13, wherein the at least one conductive line is located on a first surface of the interposer, and the at least one testing element is located on a second surface of the interposer opposite to the first surface. ### Claim 19 A three-dimensional integrated circuit (3DIC) comprising: a chip, wherein the chip includes at least one active device; an interposer electrically connected to the chip; at least one conductive line on at least one of the chip or the interposer, wherein the at least one conductive line traces a perimeter of the at least one of the top chip or the interposer; and at least one testing element over at least one of the chip or the interposer, wherein each of the at least one testing element is usable to determine an integrity of the at least one conductive line. ### Claim 20 (depends on 19) The 3DIC of claim 19, wherein the at least one conductive line is on the interposer, and the at least one testing element is over the chip.