# US 9,040,983 B2 · Passivation layer structure of semiconductor device and method for forming the same

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- Number: US 9,040,983 B2
- Document ID: US9040983B2
- Status: Granted
- Kind: B2
- Application number: 14/058,403
- Filed: 2013-10-21
- Published: 2014-02-13
- Granted: 2015-05-26
- Earliest claimed: 2010-10-29
- Assignees: Industrial Technology Research Institute
- Applicants: Industrial Technology Research Institute
- Inventors: Wen-Ching Sun; Tzer-Shen Lin; Sheng-Min Yu
- Web page: https://patentgrep.com/patent/US9040983B2

## CPC

- H10F 77/311: {for photovoltaic cells}
- C23C 18/1216: {Metal oxides (C23C18/1212 takes precedence)}
- C23C 18/1245: {Inorganic substrates other than metallic}
- C23C 18/1258: {Spray pyrolysis}
- C23C 18/1287: {with flow inducing means, e.g. ultrasonic}
- C23C 18/1291: {by heating of the substrate}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 62/102: {Constructional design considerations for preventing surface leakage or controlling electric field concentration}
- H10F 10/14: Photovoltaic cells having only PN homojunction potential barriers
- H10F 71/129: {Passivating}
- H10F 77/211: {for photovoltaic cells}
- H10H 20/84: Coatings, e.g. passivation layers or antireflective coatings
- H10P 14/6342: {Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- Y02E 10/547: Monocrystalline silicon PV cells
- Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

A passivation layer structure of a semiconductor device is provided, which includes a passivation layer formed of halogen-doped aluminum oxide and disposed on a semiconductor layer on a substrate, in which the semiconductor layer includes indium gallium zinc oxide (IGZO) or nitride-based III-V compounds. A method for forming the passivation layer structure of a semiconductor device is also disclosed.

## Claims

### Claim 1

A passivation layer structure of a semiconductor device, comprising:
a semiconductor layer disposed on a substrate, wherein a surface of the semiconductor layer comprises metal oxides or nitride-based III-V compounds; and
a passivation layer structure disposed on the semiconductor layer, wherein the passivation layer structure comprises a halogen-doped aluminum oxide layer including an aluminum oxide layer and at least a halogen dopant doped therein.

### Claim 2 (depends on 1)

The passivation layer structure of a semiconductor device as claimed in claim 1, wherein a halogen in the halogen-doped aluminum oxide layer comprises fluorine, chlorine, bromine, or iodine.

### Claim 3 (depends on 1)

The passivation layer structure of a semiconductor device as claimed in claim 1, wherein the halogen-doped aluminum oxide layer has a thickness between 10 nm and 400 nm.

### Claim 4 (depends on 1)

The passivation layer structure of a semiconductor device as claimed in claim 1, wherein a doping concentration of halogen in the halogen-doped aluminum oxide layer is between 0.01% and about 5%.

### Claim 5 (depends on 1)

The passivation layer structure of a semiconductor device as claimed in claim 1, wherein the nitride-based III-V compounds comprises gallium nitride or aluminum gallium nitride.

### Claim 6 (depends on 1)

The passivation layer structure of a semiconductor device as claimed in claim 1, wherein the substrate comprises silicon, silicon carbide, sapphire, or glass.

### Claim 7 (depends on 1)

The passivation layer structure of a semiconductor device as claimed in claim 1, wherein the semiconductor device comprises a thin film transistor, a high electron mobility transistor, a light-emitting diode, a photodiode, or a pH sensor.

### Claim 8 (depends on 1)

The passivation layer structure of a semiconductor device as claimed in claim 1, wherein the metal oxides comprises indium gallium zinc oxide, hafnium indium zinc oxide, indium tin oxide, zinc oxide, aluminum doped zinc oxide, antimony doped tin oxide, tin doped zinc oxide or fluorine doped tin oxide.

### Claim 9 (depends on 1)

A method for forming the passivation layer structure of a semiconductor device as claimed in claim 1, wherein the formation of the halogen-doped aluminum oxide layer comprises:
applying a solution on the surface of the semiconductor layer, wherein the solution comprises an aluminum-containing compound solution and a halogen-containing compound solution; and
heating the semiconductor layer to a temperature, such that the solution transforms into the halogen-doped aluminum oxide layer.

### Claim 10 (depends on 9)

The method as claimed in claim 9, wherein the aluminum-containing compound solution comprises aluminum acetylacetonate, aluminum chloride, aluminum nitrate, trimethyl aluminum, or combinations thereof.

### Claim 11 (depends on 9)

The method as claimed in claim 9, wherein the halogen-containing compound solution comprises ammonium fluoride, hydrofluoric acid, ammonium chloride, hydrochloric acid, ammonium bromide, hydrobromic acid, or combinations thereof.

### Claim 12 (depends on 9)

The method as claimed in claim 9, wherein the solution is applied on the surface of the semiconductor layer by a spray coating process or a spin coating process.

### Claim 13 (depends on 9)

The method as claimed in claim 9, wherein the temperature is between 100° C. and 500° C.

### Claim 14

A passivation layer structure of a high electron mobility transistor, comprising:
a semiconductor layer disposed on a substrate, wherein a surface of the semiconductor layer comprises intrinsic or n-type III-V compounds; and
a passivation layer structure disposed on the semiconductor layer, wherein the passivation layer structure comprises a halogen-doped aluminum oxide layer including an aluminum oxide layer and at least a halogen dopant doped therein.

### Claim 15 (depends on 14)

The passivation layer structure of a high electron mobility transistor as claimed in claim 14, wherein a halogen in the halogen-doped aluminum oxide layer comprises fluorine, chlorine, bromine, or iodine.

### Claim 16 (depends on 14)

The passivation layer structure of a high electron mobility transistor as claimed in claim 14, wherein the halogen-doped aluminum oxide layer has a thickness between 10 nm and 400 nm.

### Claim 17 (depends on 14)

The passivation layer structure of a high electron mobility transistor as claimed in claim 14, wherein a doping concentration of halogen in the halogen-doped aluminum oxide layer is between 0.01% and about 5%.

### Claim 18 (depends on 14)

The passivation layer structure of a high electron mobility transistor as claimed in claim 14, wherein the intrinsic or n-type III-V compounds comprises gallium arsenide, aluminum gallium arsenide or indium aluminum arsenide.

### Claim 19 (depends on 14)

The passivation layer structure of a high electron mobility transistor as claimed in claim 14, wherein the substrate comprises silicon or gallium arsenide.

### Claim 20 (depends on 14)

A method for forming the passivation layer structure of a high electron mobility transistor as claimed in claim 14, wherein the formation of the halogen-doped aluminum oxide layer comprises:
applying a solution on the surface of the semiconductor layer, wherein the solution comprises an aluminum-containing compound solution and a halogen-containing compound solution; and
heating the semiconductor layer to a temperature, such that the solution transforms into the halogen-doped aluminum oxide layer.

### Claim 21 (depends on 20)

The method as claimed in claim 20, wherein the aluminum-containing compound solution comprises aluminum acetylacetonate, aluminum chloride, aluminum nitrate, trimethyl aluminum, or combinations thereof.

### Claim 22 (depends on 20)

The method as claimed in claim 20, wherein the halogen-containing compound solution comprises ammonium fluoride, hydrofluoric acid, ammonium chloride, hydrochloric acid, ammonium bromide, hydrobromic acid, or combinations thereof.

### Claim 23 (depends on 20)

The method as claimed in claim 20, wherein the solution is applied on the surface of the semiconductor layer by a spray coating process or a spin coating process.

### Claim 24 (depends on 20)

The method as claimed in claim 20, wherein the temperature is between 100° C. and 500° C.