# US 9,040,980 B2 · Transistor with an oxide semiconductor layer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,040,980 B2
- Document ID: US9040980B2
- Status: Granted
- Kind: B2
- Application number: 13/046,931
- Filed: 2011-03-14
- Published: 2011-09-29
- Granted: 2015-05-26
- Earliest claimed: 2010-03-26
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Masami Endo
- Inventors: Masami Endo
- Web page: https://patentgrep.com/patent/US9040980B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6733: {Multi-gate TFTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

It is an object to provide a semiconductor device for high power application which has good properties. A means for solving the above-described problem is to form a transistor described below. The transistor includes a source electrode layer; an oxide semiconductor layer in contact with the source electrode layer; a drain electrode layer in contact with the oxide semiconductor layer; a gate electrode layer part of which overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and a gate insulating layer in contact with an entire surface of the gate electrode layer.

## Claims

### Claim 1

A transistor comprising:
a source electrode layer;
an oxide semiconductor layer in contact with the source electrode layer;
a drain electrode layer in contact with the oxide semiconductor layer;
a first gate electrode layer,
wherein part of the first gate electrode layer overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer;
a second gate electrode layer,
wherein part of the second gate electrode layer overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer;
a first gate insulating layer in contact with a surface of the first gate electrode layer; and
a second gate insulating layer in contact with a surface of the second gate electrode layer,
wherein the first gate insulating layer on a bottom surface side of the first gate electrode layer is in contact with the source electrode layer,
wherein the second gate insulating layer on a bottom surface side of the second gate electrode layer is in contact with the source electrode layer,
wherein the first gate insulating layer on an upper surface side of the first gate electrode layer is in contact with the oxide semiconductor layer, and
wherein the second gate insulating layer on an upper surface side of the second gate electrode layer is in contact with the oxide semiconductor layer,
wherein the first gate electrode layer has a first comb-shaped electrode and the second gate electrode layer has a second comb-shaped electrode,
wherein first side surfaces of the first comb-shaped electrode and second side surfaces of the second comb-shaped electrode have tapered shapes,
wherein one of the first side surfaces and one of the second side surfaces are opposed to each other, and
wherein the oxide semiconductor layer and a part of the drain electrode layer is interposed between the one of the first side surfaces of the first comb-shaped electrode and the one of the second side surfaces of the second comb-shaped electrode.

### Claim 2 (depends on 1)

The transistor according to claim 1, wherein the first gate electrode layer and the second gate electrode layer are a pair of gate electrode layers which face each other with the oxide semiconductor layer interposed therebetween, and the first gate insulating layer and the second gate insulating layer are a pair of gate insulating layers which face each other with the oxide semiconductor layer interposed therebetween.

### Claim 3

A transistor comprising:
a source electrode layer;
an oxide semiconductor layer comprising indium, gallium and zinc in contact with the source electrode layer;
a drain electrode layer in contact with the oxide semiconductor layer;
a first gate electrode layer,
wherein part of the first gate electrode layer overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer;
a second gate electrode layer,
wherein part of the second gate electrode layer overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer;
a first gate insulating layer in contact with a surface of the first gate electrode layer; and
a second gate insulating layer in contact with a surface of the second gate electrode layer,
wherein the first gate insulating layer on a bottom surface side of the first gate electrode layer is in contact with the source electrode layer,
wherein the second gate insulating layer on a bottom surface side of the second gate electrode layer is in contact with the source electrode layer,
wherein the first gate insulating layer on an upper surface side of the first gate electrode layer is in contact with the oxide semiconductor layer, and
wherein the second gate insulating layer on an upper surface side of the second gate electrode layer is in contact with the oxide semiconductor layer,
wherein the first gate electrode layer has a first comb-shaped electrode and the second gate electrode layer has a second comb-shaped electrode,
wherein first side surfaces of the first comb-shaped electrode and second side surfaces of the second comb-shaped electrode have tapered shapes,
wherein one of the first side surfaces and one of the second side surfaces are opposed to each other, and
wherein the oxide semiconductor layer and a part of the drain electrode layer is interposed between the one of the first side surfaces of the first comb-shaped electrode and the one of the second side surfaces of the second comb-shaped electrode.

### Claim 4 (depends on 1)

The transistor according to claim 1, wherein the source electrode layer or the drain electrode layer comprises a single layer or a stacked layer each comprising a metal material selected from the group consisting of molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium and nickel, or an alloy material which includes any materials selected from the group consisting of molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium and nickel.

### Claim 5 (depends on 3)

The transistor according to claim 3, wherein the source electrode layer or the drain electrode layer comprises a single layer or a stacked layer each comprising a metal material selected from the group consisting of molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium and nickel, or an alloy material which includes any materials selected from the group consisting of molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium and nickel.

### Claim 6 (depends on 1)

The transistor according to claim 1, wherein the source electrode layer or the drain electrode layer comprises a single layer or a stacked layer each comprising a material selected from the group consisting of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide and indium tin oxide.

### Claim 7 (depends on 3)

The transistor according to claim 3, wherein the source electrode layer or the drain electrode layer comprises a single layer or a stacked layer each comprising a material selected from the group consisting of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide and indium tin oxide.

### Claim 8 (depends on 1)

The transistor according to claim 1, wherein a thickness of the oxide semiconductor layer is greater than or equal to 30 nm and less than or equal to 1 μm.

### Claim 9 (depends on 3)

The transistor according to claim 3, wherein a thickness of the oxide semiconductor layer is greater than or equal to 30 nm and less than or equal to 1 μm.

### Claim 10 (depends on 1)

The transistor according to claim 1, wherein a concentration of hydrogen in the oxide semiconductor layer is lower than or equal to 5×1019 atoms/cm3.

### Claim 11 (depends on 3)

The transistor according to claim 3, wherein a concentration of hydrogen in the oxide semiconductor layer is lower than or equal to 5×1019 atoms/cm3.

### Claim 12 (depends on 1)

The transistor according to claim 1, wherein the first gate insulating layer or the second gate insulating layer comprises a single layer or a stacked layer each comprising a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, tantalum oxide and gallium oxide.

### Claim 13 (depends on 3)

The transistor according to claim 3, wherein the first gate insulating layer or the second gate insulating layer comprises a single layer or a stacked layer each comprising a material selected from the group consisting of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, a tantalum oxide film and a gallium oxide film.