# US 9,040,960 B2 · Heterojunction tunneling field effect transistors, and methods for fabricating the same

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- Number: US 9,040,960 B2
- Document ID: US9040960B2
- Status: Granted
- Kind: B2
- Application number: 13/435,994
- Filed: 2012-03-30
- Published: 2012-08-02
- Granted: 2015-05-26
- Earliest claimed: 2006-02-01
- Assignees: International Business Machines Corporation
- Applicants: Xiangdong Chen; Haining S. Yang
- Inventors: Xiangdong Chen; Haining S. Yang
- Web page: https://patentgrep.com/patent/US9040960B2

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 12/021: {of gated diodes, e.g. field-controlled diodes [FCD]}
- H10D 12/211: {Gated diodes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.

## Claims

### Claim 1

A tunneling field effect transistor (TFET) comprising:
a drain region that comprises silicon of an n-type conductivity;
a source region spaced apart from the drain region, wherein said source region comprises silicon germanium of a p-type conductivity;
a channel region located between the source and drain regions, wherein the channel region has an n-type conductivity; and
a gate stack located over the channel region, wherein said gate stack comprises a gate dielectric and a gate conductor,
wherein the source region has a graded germanium content profile that gradually decreases in a direction away from a junction immediately adjacent to the channel region, wherein germanium concentration at said junction immediately adjacent to the channel region ranges from about 10 atomic % to about 30 atomic %.

### Claim 2 (depends on 1)

The TFET of claim 1, wherein the source, drain, and channel regions are located in a p-well of a semiconductor substrate.

### Claim 3 (depends on 1)

The TFET of claim 1, wherein the channel region has a channel length ranging from about 0.2 μm to about 10 μm.

### Claim 4 (depends on 3)

The TFET of claim 3, wherein the channel region has a channel width ranging from about 0.02 μm to about 10 μm.

### Claim 5 (depends on 1)

The TFET of claim 1, wherein the source region that comprises silicon germanium of the p-type conductivity has a larger band gap than silicon.

### Claim 6 (depends on 1)

The TFET of claim 1, wherein a semiconductor substrate in which the source region, the drain region and the channel region are provided is a silicon on insulator (SOI) substrate.

### Claim 7 (depends on 6)

The TFET of claim 6, further comprising at least one isolation region provided in the semiconductor substrate.