# US 9,040,958 B2 · Transistors and methods of manufacturing the same

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- Number: US 9,040,958 B2
- Document ID: US9040958B2
- Status: Granted
- Kind: B2
- Application number: 13/792,525
- Filed: 2013-03-11
- Published: 2014-01-23
- Granted: 2015-05-26
- Earliest claimed: 2012-07-23
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Chang-seung Lee; Yong-sung Kim; Joo-ho Lee; Yong-seok Jung
- Web page: https://patentgrep.com/patent/US9040958B2

## CPC

- H10D 62/882: {Graphene}
- H10D 30/01: Manufacture or treatment
- H10D 30/017: {of FETs having two-dimensional material channels, e.g. TMD FETs}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/8303: {Diamond}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Transistors, and methods of manufacturing the transistors, include graphene and a material converted from graphene. The transistor may include a channel layer including graphene and a gate insulating layer including a material converted from graphene. The material converted from the graphene may be fluorinated graphene. The channel layer may include a patterned graphene region. The patterned graphene region may be defined by a region converted from graphene. A gate of the transistor may include graphene.

## Claims

### Claim 1

A transistor, comprising:
a channel layer including graphene;
a gate insulating layer on a surface of the channel layer, the gate insulating layer including fluorinated graphene;
a gate facing the channel layer, the gate insulating layer being between the gate and the channel layer; and
a source and a drain electrically connected to first and second regions of the channel layer, respectively.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein the gate includes graphene.

### Claim 3 (depends on 1)

The transistor of claim 1, wherein,
the channel layer includes a patterned graphene region, and
the patterned graphene region is a nanoscale patterned region.

### Claim 4 (depends on 3)

The transistor of claim 3, wherein,
the channel layer includes a fluorinated graphene region and a non-fluorinated graphene region, and
the non-fluorinated graphene region corresponds to the patterned graphene region.

### Claim 5 (depends on 3)

The transistor of claim 3, wherein the patterned graphene region includes a graphene nanoribbon (GNR) region.

### Claim 6 (depends on 3)

The transistor of claim 3, wherein the patterned graphene region includes a graphene nanomesh (GNM) region.

### Claim 7 (depends on 1)

The transistor of claim 1, wherein the channel layer is a single-layer graphene.

### Claim 8 (depends on 1)

The transistor of claim 1, wherein the gate insulating layer is a fluorinated single-layer graphene.

### Claim 9 (depends on 1)

The transistor of claim 1, wherein the gate insulating layer further comprises an insulating layer between the fluorinated graphene and the gate.

### Claim 10 (depends on 1)

The transistor of claim 1, wherein,
the gate insulating layer is on a portion of the channel layer,
the source is on the channel layer at one side of the gate insulating layer, and
the drain is on the channel layer at another side of the gate insulating layer.

### Claim 11 (depends on 10)

The transistor of claim 10, further comprising:
a first graphene region between the channel layer and the source; and
a second graphene region between the channel layer and the drain.

### Claim 12

A transistor, comprising:
a channel layer including a region comprised of graphene with a chemical modifier attached and a patterned graphene region defined by the region;
a gate insulating layer on a surface of the channel layer, the gate insulating layer including fluorinated graphene;
a gate facing the channel layer, the gate insulating layer being between the gate and the channel layer; and
a source and a drain electrically connected to first and second regions of the channel layer, respectively.

### Claim 13 (depends on 12)

The transistor of claim 12, wherein the region comprised of graphene with a chemical modifier attached is chemically converted from graphene without the chemical modifier attached.

### Claim 14 (depends on 12)

The transistor of claim 12, wherein the region comprised of graphene with a chemical modifier attached is a fluorinated graphene region.

### Claim 15 (depends on 12)

The transistor of claim 12, wherein the patterned graphene region includes a graphene nanoribbon (GNR) region or a graphene nanomesh (GNM) region.

### Claim 16 (depends on 12)

The transistor of claim 12, wherein the gate includes graphene.

### Claim 17

A transistor, comprising:
a channel layer, a gate insulating layer, a gate, a source, and a drain,
wherein the channel layer, the gate insulating layer, and the gate include at least one of graphene and a material comprised of graphene with a chemical modifier attached.

### Claim 18 (depends on 17)

The transistor of claim 17, wherein the material comprised of graphene with a chemical modifier attached is chemically converted from graphene without a chemical modifier attached.

### Claim 19 (depends on 17)

The transistor of claim 17, wherein the gate insulating layer includes fluorinated graphene.

### Claim 20 (depends on 17)

The transistor of claim 17, wherein the channel layer includes graphene.

### Claim 21 (depends on 20)

The transistor of claim 20, wherein the channel layer includes a fluorinated graphene region and a patterned graphene region defined by the fluorinated graphene region.

### Claim 22 (depends on 17)

The transistor of claim 17, wherein the gate includes graphene.