# US 9,040,957 B2 · Field effect transistor using graphene

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- Number: US 9,040,957 B2
- Document ID: US9040957B2
- Status: Granted
- Kind: B2
- Application number: 13/772,693
- Filed: 2013-02-21
- Published: 2014-01-16
- Granted: 2015-05-26
- Earliest claimed: 2012-07-16
- Assignees: Samsung Electronics Co., Ltd.; Seoul National University R&Db Foundation
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jae-ho Lee; Seong-jun Park; Kyung-eun Byun; David Seo; Hyun-jae Song; Hyung-cheol Shin; Jae-hong Lee; Hyun-jong Chung; Jin-seong Heo
- Web page: https://patentgrep.com/patent/US9040957B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/01: Manufacture or treatment
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 62/8303: {Diamond}
- H10D 62/882: {Graphene}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- Y10S 977/734: Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
- Y10S 977/842: for carbon nanotubes or fullerenes
- Y10S 977/938: Field effect transistors, FETS, with nanowire- or nanotube-channel region
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.

## Claims

### Claim 1

A field effect transistor comprising:
a substrate;
a graphene channel layer on the substrate,
the graphene channel layer defining a slit;
a source electrode and a drain electrode spaced apart from each other,
the source electrode and the drain electrode being configured to apply voltages to the graphene channel layer;
a gate electrode on the graphene channel layer; and
a gate insulation layer between the graphene channel layer and the gate electrode.

### Claim 2 (depends on 1)

The field effect transistor of claim 1, further comprising:
a potential barrier material filling the slit of the graphene channel layer,
wherein the potential barrier material is configured to induce Fowler-Nordheim (F-N) tunneling through the graphene channel layer when a gate voltage is applied to the gate electrode.

### Claim 3 (depends on 2)

The field effect transistor of claim 2, wherein the potential barrier material includes undoped silicon (Si).

### Claim 4 (depends on 2)

The field effect transistor of claim 2, wherein the potential barrier material and the gate insulation layer are a same material.

### Claim 5 (depends on 1)

The field effect transistor of claim 1, wherein a width of the slit allows F-N tunneling through the graphene channel layer when a gate voltage is applied to the gate electrode.

### Claim 6 (depends on 1)

The field effect transistor of claim 1, wherein the graphene channel layer defines a plurality of the slits.

### Claim 7 (depends on 1)

The field effect transistor of claim 1, wherein the gate electrode is closer to the slit of the graphene channel layer than at least one of the source electrode and the drain electrode.

### Claim 8 (depends on 1)

The field effect transistor of claim 1, wherein the source electrode is closer to the slit of the graphene channel layer than the drain electrode.

### Claim 9

A field effect transistor comprising:
a substrate;
a graphene channel layer on the substrate,
the graphene channel layer defining a slit;
a source electrode and a drain electrode on opposite ends of the graphene channel layer;
a gate electrode below the graphene channel layer; and
a gate insulation layer between the graphene channel layer and the gate electrode;
a potential barrier material filling the slit of the graphene channel layer,
the potential barrier material is configured to induce Fowler-Nordheim (F-N) tunneling through the graphene channel layer when a gate voltage is applied to the gate electrode.

### Claim 10 (depends on 9)

The field effect transistor of claim 9, wherein the potential barrier material includes undoped silicon (Si).

### Claim 11

A field effect transistor comprising:
a substrate;
a graphene channel layer on the substrate,
the graphene channel layer defining at least one slit;
a source electrode and a drain electrode that are spaced apart on at least one of the graphene layer and the substrate;
a gate electrode on the substrate;
a gate insulation layer between the gate electrode and the graphene channel layer.

### Claim 12 (depends on 11)

The field effect transistor of claim 11, further comprising:
a potential barrier material, wherein
the at least one slit is one slit in the graphene channel layer,
the potential barrier material fills the slit of the graphene channel layer, and
the potential barrier material is configured to induce Fowler-Nordheim (F-N) tunneling through the graphene channel layer when a gate voltage is applied to the gate electrode.

### Claim 13 (depends on 12)

The field effect transistor of claim 12, wherein the potential barrier material and the gate insulation layer are a same material.

### Claim 14 (depends on 11)

The field effect transistor of claim 11, wherein
the at least one slit is one slit in the graphene channel layer, and
the slit of the graphene channel layer is closer to one of the source electrode and the drain electrode compared to an other of the source electrode and the drain electrode.

### Claim 15 (depends on 11)

The field effect transistor of claim 11, wherein the graphene channel layer is about one to about three carbon layers in thickness.

### Claim 16 (depends on 11)

The field effect transistor of claim 11, wherein the gate electrode is between the source electrode and the drain electrode.