# US 9,040,843 B2 · Multilayer printed wiring board > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,040,843 B2 - Document ID: US9040843B2 - Status: Granted - Kind: B2 - Application number: 13/617,012 - Filed: 2012-09-14 - Published: 2013-01-10 - Granted: 2015-05-26 - Earliest claimed: 2001-03-14 - Assignees: Ibiden Co., Ltd. - Applicants: Yukihiko Toyoda; Yoichiro Kawamura; Tomoyuki Ikeda - Inventors: Yukihiko Toyoda; Yoichiro Kawamura; Tomoyuki Ikeda - Web page: https://patentgrep.com/patent/US9040843B2 ## CPC - H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)} - H05K 1/0271: {Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion} - H05K 1/113: {Via provided in pad; Pad over filled via} - H05K 1/116: {Lands, clearance holes or other lay-out details concerning the surrounding of a via} - H05K 3/4688: {Composite multilayer circuits, i.e. comprising insulating layers having different properties (having a special base or central core H05K3/4602)} - H10W 70/095: {of vias therein} - H10W 70/635: {Through-vias} - H05K 3/28: Applying non-metallic protective coatings {(H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673)} - H05K 3/4602: {characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated} - H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)} - H05K 3/4661: {Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor (other insulating materials H05K3/387)} - H05K 2201/0133: Elastomeric or compliant polymer - H05K 2201/0209: Inorganic, non-metallic particles - H05K 2201/0212: Resin particles - H05K 2201/068: wherein the coefficient of thermal expansion is important - H05K 2201/09454: Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB - H05K 2201/09536: Buried plated through-holes, i.e. plated through-holes formed in a core before lamination - H05K 2201/09563: Metal filled via - H05K 2201/096: Vertically aligned vias, holes or stacked vias - H05K 2201/09627: Special connections between adjacent vias, not for grounding vias - H05K 2201/09745: Recess in conductor, e.g. in pad or in metallic substrate - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A multilayered printed circuit board including a substrate, a multilayered structure formed on the substrate and including multiple conductor circuits and multiple interlaminar resin insulating layers, and a stack-via structure having multiple via-holes and formed in the multilayered structure such that the via-holes are piled through the interlaminar resin insulating layers in the multilayered structure. The interlaminar resin insulating layers include an outermost interlaminar resin insulating layer forming an outermost layer of the interlaminar resin insulating layers and having a coefficient of linear expansion which is equal to or smaller than coefficients of linear expansion of the interlaminar resin insulating layers other than the outermost interlaminar resin insulating layer. ## Claims ### Claim 1 A multilayered printed circuit board, comprising: a substrate; a multilayered structure formed on the substrate and comprising a plurality of conductor circuits and a plurality of interlaminar resin insulating layers; and a stack-via structure comprising a plurality of via-holes and formed in the multilayered structure such that the via-holes are piled through the interlaminar resin insulating layers in the multilayered structure, wherein each of the via-holes has a filled via structure portion comprising a metal portion such that the metal portion is filling an opening of a respective one of the interlaminar resin insulating layers, the plurality of via-holes of the stack-via structure includes an outermost via-hole of the stack-via structure, and the outermost via-hole of the stack-via structure has a recess portion on an outer surface of the outermost via-hole. ### Claim 2 (depends on 1) The multilayered printed circuit board according to claim 1, wherein the plurality of interlaminar resin insulating layers includes an outermost interlaminar resin insulating layer having a coefficient of linear expansion which is equal to or smaller than coefficients of linear expansion of the interlaminar resin insulating layers other than the outermost interlaminar resin insulating layer. ### Claim 3 (depends on 1) The multilayered printed circuit board according to claim 1, wherein the plurality of via-holes is formed such that the via-holes are directly stacked one another. ### Claim 4 (depends on 3) The multilayered printed circuit board according to claim 3, wherein the plurality of interlaminar resin insulating layers includes an outermost interlaminar resin insulating layer having a coefficient of linear expansion which is equal to or smaller than coefficients of linear expansion of the interlaminar resin insulating layers other than the outermost interlaminar resin insulating layer. ### Claim 5 (depends on 4) The multilayered printed circuit board according to claim 4, further comprising a solder resist layer formed on the multilayered structure. ### Claim 6 (depends on 3) The multilayered printed circuit board according to claim 3, further comprising a solder resist layer formed on the multilayered structure. ### Claim 7 (depends on 1) The multilayered printed circuit board according to claim 1, wherein the plurality of via-holes includes at least one via-hole having a center deviated from an axis of said stack-via structure. ### Claim 8 (depends on 7) The multilayered printed circuit board according to claim 7, further comprising a solder resist layer formed on the multilayered structure. ### Claim 9 (depends on 1) The multilayered printed circuit board according to claim 1, further comprising a solder resist layer formed on the multilayered structure. ### Claim 10 (depends on 1) The multilayered printed circuit board according to claim 1, wherein the conductor circuits are formed on the interlaminar resin insulating layers, respectively, such that the conductor circuits and the interlaminar resin insulating layers are formed alternately, and the conductor circuits are connected by the stack-via structure through interlaminar resin insulating layers. ### Claim 11 (depends on 10) The multilayered printed circuit board according to claim 10, wherein the plurality of via-holes is formed such that the via-holes are directly stacked one another. ### Claim 12 (depends on 10) The multilayered printed circuit board according to claim 10, wherein the plurality of via-holes includes at least one via-hole having a center deviated from an axis of said stack-via structure. ### Claim 13 (depends on 10) The multilayered printed circuit board according to claim 10, wherein the plurality of interlaminar resin insulating layers includes an outermost interlaminar resin insulating layer having a coefficient of linear expansion which is equal to or smaller than coefficients of linear expansion of the interlaminar resin insulating layers other than the outermost interlaminar resin insulating layer. ### Claim 14 (depends on 1) The multilayered printed circuit board according to claim 1, further comprising: a solder resist layer formed on the multilayered structure, wherein the conductor circuits are formed on the interlaminar resin insulating layers, respectively, such that the conductor circuits and the interlaminar resin insulating layers are formed alternately, and the conductor circuits are connected by the stack-via structure through interlaminar resin insulating layers. ### Claim 15 (depends on 1) The multilayered printed circuit board according to claim 1, wherein the plurality of via-holes is formed such that the via-holes are directly stacked one another such that the via-hole is aligned with respect to the plurality of via-holes of the stack-via structure. ### Claim 16 (depends on 15) The multilayered printed circuit board according to claim 15, further comprising: a solder resist layer formed on the multilayered structure, wherein the conductor circuits are formed on the interlaminar resin insulating layers, respectively, such that the conductor circuits and the interlaminar resin insulating layers are formed alternately, and the conductor circuits are connected by the stack-via structure through interlaminar resin insulating layers. ### Claim 17 (depends on 15) The multilayered printed circuit board according to claim 15, further comprising: a solder resist layer formed on the multilayered structure. ### Claim 18 (depends on 1) The multilayered printed circuit board according to claim 1, wherein the plurality of conductor circuits includes at least one conductor circuits connected to the stack-via structure. ### Claim 19 (depends on 1) The multilayered printed circuit board according to claim 1, wherein the plurality of via-holes is formed such that the via-holes are directly stacked one another on the filled via structure portion of each of the via-holes. ### Claim 20 (depends on 1) The multilayered printed circuit board according to claim 1, wherein each of the via-holes has a land portion formed on the respective one of the interlaminar resin insulating layers. ### Claim 21 (depends on 1) The multilayered printed circuit board according to claim 1, further comprising: a solder bump formed on the recess portion of the outermost via-hole. ### Claim 22 (depends on 1) The multilayered printed circuit board according to claim 1, wherein the plurality of via-holes of the stack-via structure includes at least one via-hole positioned such that the via-hole is not aligned with respect to the plurality of via-holes of the stack-via structure.