# US 9,040,838 B2 · Method for forming solder resist and substrate for package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,040,838 B2 - Document ID: US9040838B2 - Status: Granted - Kind: B2 - Application number: 14/011,159 - Filed: 2013-08-27 - Published: 2014-02-27 - Granted: 2015-05-26 - Earliest claimed: 2012-08-27 - Assignees: Samsung Electro-Mechanics Co., Ltd. - Applicants: Samsung Electro-Mechanics Co., Ltd. - Inventors: Chang Bo Lee; Chang Sup Ryu; Hyo Bin Park; Cheol Ho Choi - Web page: https://patentgrep.com/patent/US9040838B2 ## CPC - H05K 1/0296: {Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295 (H05K1/11 takes precedence; lay-out adapted to mounted component configuration H05K1/18)} - H05K 3/0023: {by exposure and development of a photosensitive insulating layer} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage} - H05K 3/3452: Solder masks - H05K 2203/058: Additional resists used for the same purpose but in different areas, i.e. not stacked - H05K 2203/0597: Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating - H05K 2203/1173: Differences in wettability, e.g. hydrophilic or hydrophobic areas - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present invention relates to a method for forming solder resist and a substrate for a package. The method for forming solder resist including: forming a first solder resist inner region by primarily coating, exposing, and developing a solder resist on a substrate on which an outer PoP pad and an inner chip pad are formed, and removing the solder resist's outer portion on the substrate's outer region and curing the solder resist's inner portion on the substrate's inner region; forming a plugged SR region which does not expose the substrate; changing a surface roughness by performing a desmear process on a surface of the first solder resist inner region in which the plugged SR region is formed; and forming a second solder resist SMD region which covers an edge of the PoP pad, exposing, and developing the solder resist on the substrate after the desmear process is provided. ## Claims ### Claim 1 A substrate for a package comprising: a substrate; a circuit pattern formed on the substrate and comprising an outer package-on-package (PoP) pad for mounting an upper package thereon and a chip pad for mounting an inner chip thereon; a first solder resist (SR) inner region formed by being coated on an inner region of the substrate on which the inner circuit pattern comprising the chip pad is formed, comprising a plugged SR region which does not expose the substrate while exposing the entire upper surface of the chip pad by laser ablation, and desmeared to have a changed surface roughness; and a second solder resist SMD region formed to cover an edge of the first solder resist inner region and an edge of the POP pad and having a surface roughness different from a surface roughness of the plugged SR region on the first solder resist inner region. ### Claim 2 (depends on 1) The substrate for a package according to claim 1, wherein the surface roughness of the plugged SR region on the first solder resist inner region is higher than the surface roughness of the second solder resist SMD region. ### Claim 3 (depends on 1) The substrate for a package according to claim 1, wherein the inner circuit pattern comprising the chip pad further comprises a bump pad formed around the chip pad, the first solder resist inner region is formed on the inner region of the substrate on which the inner circuit pattern comprising the chip pad and the bump pad is formed, and the plugged SR region is formed by laser ablation not to expose the substrate while exposing the entire upper surface of the chip pad and the bump pad. ### Claim 4 (depends on 1) The substrate for a package according to claim 1, wherein a height of the plugged SR region is lower than a height of the upper surface of the chip pad. ### Claim 5 (depends on 1) The substrate for a package according to claim 1, wherein a height of the second solder resist SMD region is higher than a height of the first solder resist inner region. ### Claim 6 (depends on 1) The substrate for a package according to claim 1, wherein the first solder resist inner region and the second solder resist SMD region are made of one of a photocurable resin, a thermosetting resin, and photocurable and thermosetting resins.