# US 9,040,836 B2 · Multilayered wiring board and method for fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,040,836 B2 - Document ID: US9040836B2 - Status: Granted - Kind: B2 - Application number: 13/482,784 - Filed: 2012-05-29 - Published: 2012-11-22 - Granted: 2015-05-26 - Earliest claimed: 2005-08-29 - Assignees: Shinko Electric Industries Co., Ltd. - Applicants: Junichi Nakamura; Yuji Kobayashi; Mikio Yamagiwa - Inventors: Junichi Nakamura; Yuji Kobayashi; Mikio Yamagiwa - Web page: https://patentgrep.com/patent/US9040836B2 ## CPC - H05K 1/0366: {reinforced, e.g. by fibres, fabrics (H05K1/036 takes precedence)} - H05K 1/036: {Multilayers with layers of different types} - H05K 3/4602: {characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated} - H05K 3/4655: {by using a laminate characterized by the insulating layer (general-purpose insulating materials H05K1/03, H05K3/4673)} - H05K 3/4673: {Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer (similar methods for protective coatings H05K3/28)} - H05K 3/4682: {Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil} - H05K 3/4688: {Composite multilayer circuits, i.e. comprising insulating layers having different properties (having a special base or central core H05K3/4602)} - H10P 72/74: {using temporarily an auxiliary support} - H05K 3/205: {using a pattern electroplated or electroformed on a metallic carrier} - H05K 3/423: {characterised by electroplating method} - H05K 2203/0152: Temporary metallic carrier, e.g. for transferring material - H05K 2203/0733: Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls - H05K 2203/1536: Temporarily stacked PCBs - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10W 70/655: Fan-out layouts - H10W 70/682: {comprising holes having chips therein} - H10W 70/685: comprising multiple insulating layers - H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - Y10T 29/49126: Assembling bases - Y10T 29/49155: Manufacturing circuit on or in base - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract In a multilayered wiring board constituted by laminating to form pluralities of layers of wiring layers 105, 108, 110 and insulating layers 104, 106, 107, in the plurality of laminated insulating layers 104, 106, 107, the insulating layer 106 disposed at a laminating center in a laminating direction is made to constitute an insulating layer with a reinforcing member including a reinforcing member. ## Claims ### Claim 1 A wiring board comprising: a reinforced insulating layer containing (i) a reinforcing material including a woven cloth or a non-woven cloth and (ii) a resin material therein, the reinforcing material being impregnated by the resin material, the reinforced insulating layer comprising a first surface and a second surface opposite to the first surface; a first multilayer wiring structure disposed on the first surface of the reinforced insulating layer and comprising a first inner surface facing the first surface of the reinforced insulating layer and a first outer surface opposite to the first inner surface, the first multilayer wiring structure comprising: a plurality of first insulating layers each containing a material that consists of the same resin material as the reinforced insulating layer and does not include the reinforcing material; and a plurality of first wiring layers, a second multilayer wiring structure disposed on the second surface of the reinforced insulating layer and comprising a second inner surface facing the second surface of the reinforced insulating layer and a second outer surface opposite to the second inner surface, the second multilayer wiring structure comprising: a plurality of second insulating layers each containing a material that consists of the same resin material as the reinforced insulating layer and does not include the reinforcing material; and a plurality of second wiring layers, wherein a first electrode pad is disposed on the first outer surface of the first multilayer wiring structure, a second electrode pad is disposed on the second outer surface of the second multilayer wiring structure, a thickness of the reinforced insulating layer is 100 μm or less, and a thickness of each of the first and second insulating layers is 15-35 μm. ### Claim 2 (depends on 1) The wiring board of claim 1, further comprising: a solder resist layer disposed on the second outer surface of the second multilayer wiring structure such that the second electrode pad is exposed from the solder resist layer. ### Claim 3 (depends on 1) The wiring board of claim 1, wherein the reinforced insulating layer comprises a through via formed therethrough, and the first electrode pad and the second electrode pad are electrically connected to each other through the through via. ### Claim 4 (depends on 1) A semiconductor package comprising: the wiring board of claim 1; and a semiconductor chip mounted on the wiring board. ### Claim 5 (depends on 1) The wiring board of claim 1, wherein the thickness of the reinforced insulating layer is 15 μm-100 μm. ### Claim 6 (depends on 1) The wiring board of claim 1, wherein the thickness of the reinforced insulating layer is larger than the thickness of each of first and second insulating layers. ### Claim 7 (depends on 1) The wiring board of claim 1, wherein the reinforced insulating layer is higher in mechanical strength that the first and second insulating layers. ### Claim 8 A method of manufacturing a wiring board, the method comprising: (a) providing a support member; (b) forming a first multilayer wiring structure on the support member, wherein the first multilayer wiring structure comprises: a plurality of first insulating layers each having a thickness of 15-35 μm; and a plurality of first wiring layers, (c) forming a reinforced insulating layer containing (i) a reinforcing material including a woven cloth or a non-woven cloth and (ii) a resin material therein on the first multilayer wiring structure, the reinforcing material being impregnated by the resin material, the reinforced insulating layer having a thickness of 100 μm or less; (d) forming a second multilayer wiring structure on the reinforced insulating layer, wherein the second multilayer wiring structure comprises: a plurality of second insulating layers each containing a material that consists of the same resin material as the reinforced insulating layer and does not include the reinforcing material, each second insulating layer having a thickness of 15-35 μm; and a plurality of second wiring layers, (e) removing the support member, wherein each first insulating layer contains a material that consists of the same resin material as the reinforced insulating layer and does not include the reinforcing material. ### Claim 9 (depends on 8) The method of claim 8, further comprising: (f) forming a solder resist layer on the second multilayer wiring structure. ### Claim 10 (depends on 8) The method of claim 8, further comprising: (g) forming a through hole through the reinforced insulating layer; and (h) filling the through hole with a metal material to form a through via in the reinforced insulating layer. ### Claim 11 (depends on 8) The method of claim 8, wherein the thickness of the reinforced insulating layer is 15 μm-100 μm. ### Claim 12 (depends on 8) The method of claim 8, wherein the thickness of the reinforced insulating layer is larger than the thickness of each of first and second insulating layers. ### Claim 13 (depends on 8) The method of claim 8, wherein the reinforced insulating layer is higher in mechanical strength that the first and second insulating layers. ### Claim 14 A method of manufacturing a semiconductor package, comprising; (a) providing a support member; (b) forming a first multilayer wiring structure on the support member, wherein the first multilayer wiring structure comprises: a plurality of first insulating layers each having a thickness of 15-35 μm; and a plurality of first wiring layers, (c) forming a reinforced insulating layer containing (i) a reinforcing material and (ii) a resin material therein on the first multilayer wiring structure, the reinforcing material being impregnated by the resin material, the reinforced insulating layer having a thickness of 100 μm or less; (d) forming a second multilayer wiring structure on the reinforced insulating layer, wherein the second multilayer wiring structure comprises: a plurality of second insulating layers each containing a material that consists of the same resin material as the reinforced insulating layer and does not include the reinforcing material, each second insulating layer having a thickness of 15-35 μm; and a plurality of second wiring layers, (e) removing the support member; and (f) mounting a semiconductor chip on the second multilayer wiring structure, wherein each first insulating layer contains a material that consists of the same resin material as the reinforced insulating layer and does not include the reinforcing material. ### Claim 15 (depends on 14) The method of claim 14, wherein the thickness of the reinforced insulating layer is 15 μm-100 μm. ### Claim 16 (depends on 14) The method of claim 14, wherein the thickness of the reinforced insulating layer is larger than the thickness of each of first and second insulating layers. ### Claim 17 (depends on 14) The method of claim 14, wherein the reinforced insulating layer is higher in mechanical strength that the first and second insulating layers.