# US 9,040,832 B2 · Wiring substrate and method of manufacturing the same

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- Number: US 9,040,832 B2
- Document ID: US9040832B2
- Status: Granted
- Kind: B2
- Application number: 13/433,680
- Filed: 2012-03-29
- Published: 2012-10-04
- Granted: 2015-05-26
- Earliest claimed: 2011-03-29
- Assignees: Shinko Electric Industries Co., Ltd.
- Applicants: Yuichiro Shimizu; Ryo Fukasawa
- Inventors: Yuichiro Shimizu; Ryo Fukasawa
- Web page: https://patentgrep.com/patent/US9040832B2

## CPC

- H10W 70/685: comprising multiple insulating layers
- H05K 1/09: Use of materials for the {conductive, e.g. } metallic pattern
- H05K 3/386: {by the use of an organic polymeric bonding layer, e.g. adhesive}
- H05K 3/388: {by the use of a metallic or inorganic thin film adhesion layer}
- H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H05K 3/108: {by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241)}
- H05K 3/389: {by the use of a coupling agent, e.g. silane}
- H05K 2203/0338: Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A method of manufacturing a wiring substrate, includes obtaining a laminated body in which a first copper tin alloy layer and a copper layer are arranged in sequence on a first coupling agent layer, on a first insulating resin layer, forming a seed layer on the copper layer, forming a plating resist in which an opening portion is provided on the seed layer, forming a metal plating layer in the opening portion of the plating resist by applying an electroplating that utilizes the seed layer as a plating power feeding path, removing the plating resist, and forming a first wiring layer on the first coupling agent layer by etching the seed layer, the copper layer, and the first copper tin alloy layer while using the metal plating layer as a mask.

## Claims

### Claim 1

A wiring substrate, comprising:
a first insulating resin layer;
a first coupling agent layer formed on the first insulating resin layer;
a first wiring layer including a first copper tin alloy layer formed on the first coupling agent layer, a copper layer formed on the first copper tin alloy layer, a seed layer formed on the copper layer, and a metal plating layer formed on the seed layer; and
an underlayer wiring layer formed under the first insulating resin layer, a via hole being formed in the first insulating resin layer to reach the underlayer wiring layer,
wherein the first coupling agent layer is formed on the first insulating resin layer except the via hole, and
wherein the seed layer is formed to extend from an inner surface of the via hole onto the copper layer, and
the first wiring layer is connected to the underlayer wiring layer via the via hole.

### Claim 2 (depends on 1)

A wiring substrate according to claim 1, further comprising:
a second copper tin alloy layer formed on an upper surface and a side surface of the first wiring layer;
a second coupling agent layer covering the second copper tin alloy layer of the first wiring layer; and
a second insulating resin layer formed on the second coupling agent layer.

### Claim 3 (depends on 2)

A wiring substrate according to claim 2, further comprising:
a via hole formed in the second insulating resin layer, the second coupling agent layer, and the second copper tin alloy layer to reach the first wiring layer; and
a second wiring layer formed on the second insulating resin layer, and connected to the first wiring layer via the via hole.

### Claim 4 (depends on 3)

A wiring substrate according to claim 3, further comprising:
a third copper tin alloy layer formed on an upper surface and a side surface of the second wiring layer;
a third coupling agent layer covering the third copper tin alloy layer of the second wiring layer; and
a protection insulating layer formed on the third coupling agent layer, and in which an opening portion is provided in a part corresponding to a connection part of the second wiring layer;
wherein the third coupling agent layer and the third copper tin alloy layer located in the opening portion of the protection insulating layer are removed.