# US 9,040,426 B2 · Method for manufacturing semiconductor device

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- Number: US 9,040,426 B2
- Document ID: US9040426B2
- Status: Granted
- Kind: B2
- Application number: 13/676,717
- Filed: 2012-11-14
- Published: 2013-05-16
- Granted: 2015-05-26
- Earliest claimed: 2011-11-14
- Assignees: Sumitomo Electric Device Innovations, Inc.
- Applicants: Sumitomo Electric Device Innovations, Inc.
- Inventors: Masatoshi Koyama; Kazuaki Matsuura; Tsutomu Komatani
- Web page: https://patentgrep.com/patent/US9040426B2

## CPC

- H10D 62/103: {for increasing or controlling the breakdown voltage of reverse-biased devices}
- H10D 30/01: Manufacture or treatment
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/027: {of lateral single-gate IGFETs}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/8303: {Diamond}
- H10P 14/00: Formation of materials, e.g. in the shape of layers or pillars
- H10P 14/60: of insulating materials
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor device includes: forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region, which crosses the inactive region to electrically connect the first active region to the second active region, in a semiconductor layer; forming an insulating layer on the semiconductor layer; and forming an opening selectively in the insulating layer by dry etching.

## Claims

### Claim 1

A method for manufacturing a semiconductor device comprising:
forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region;
wherein the inactive region surrounds the first active region and the second active region surrounds the inactive region;
wherein the third active region is formed directly in the inactive region so as to directly connect the first active region to the second active region, in a semiconductor layer;
forming an insulating layer on the semiconductor layer;
forming an opening selectively in the insulating layer by dry etching.

### Claim 2 (depends on 1)

The method according to claim 1, wherein
the second active region is a scribe line.

### Claim 3 (depends on 2)

The method according to claim 2, wherein
a plurality of the first active regions are formed, and
each of the plurality of the first active regions is directly connected to the second active region by at least one of a plurality of the third active regions.

### Claim 4 (depends on 1)

The method according to claim 1, wherein
the first active region includes a layer functioning as a channel layer of a field-effect transistor, and
the second active region and the third active region have the same layer structure as the first active region has.

### Claim 5 (depends on 1)

The method according to claim 1, wherein
the insulating layer is made of silicon nitride, of which an FTIR peak position of a silicon-nitrogen stretching vibration is less than or equal to 2160 cm−1, or of aluminum oxide, of which an FTIR peak position of an aluminum-oxygen stretching vibration is greater than or equal to 960 cm−1.

### Claim 6 (depends on 1)

The method according to claim 1, wherein
the semiconductor layer is made of a nitride semiconductor.

### Claim 7 (depends on 1)

The method according to claim 1, wherein
the dry etching is performed by RIE, ICP etching, or ECR etching.

### Claim 8 (depends on 4)

The method according to claim 4, wherein
the first active region further includes an electron supply layer and a cap layer.

### Claim 9

A method for manufacturing a semiconductor device comprising:
forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region,
wherein the inactive region surrounds the first active region and the second active region surrounds the inactive region;
wherein the third active region is formed directly in the inactive region so as to directly connect the first active region to the second active region, in a semiconductor layer; and
applying dry-etching by RIE, ICP etching, or ECR etching.