# US 9,040,425 B2 · Methods of forming printable integrated circuit devices and devices formed thereby

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- Number: US 9,040,425 B2
- Document ID: US9040425B2
- Status: Granted
- Kind: B2
- Application number: 14/334,179
- Filed: 2014-07-17
- Published: 2015-03-19
- Granted: 2015-05-26
- Earliest claimed: 2009-03-26
- Assignees: Semprius, Inc.
- Applicants: Semprius, Inc.
- Inventors: Christopher Bower; Etienne Menard; Matthew Meitl; Joseph Carr
- Web page: https://patentgrep.com/patent/US9040425B2

## CPC

- H10D 86/0214: {using temporary substrates}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6746: {Amorphous silicon}
- H10D 86/01: Manufacture or treatment
- H10D 86/40: characterised by multiple TFTs
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 14/416: {of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10P 50/242: {of Group IV materials}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to selectively etch through the semiconductor active layer and the sacrificial layer in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. A step can be performed to selectively etch through the capping layer and the first portion of the semiconductor active layer to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.

## Claims

### Claim 1

A method of forming an integrated circuit device, comprising:
forming a sacrificial layer on a handling substrate;
forming a semiconductor active layer on the sacrificial layer;
selectively etching through the semiconductor active layer and the sacrificial layer to define a patterned substrate comprising a first portion of the semiconductor active layer;
forming a multi-layer electrical interconnect network on the patterned substrate;
encapsulating the multi-layer electrical interconnect network with an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer;
selectively etching through the inorganic capping layer and the first portion of the semiconductor active layer to expose the sacrificial layer; and
selectively removing the sacrificial layer from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the inorganic capping layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein said encapsulating is preceded by roughening the upper surface of the first portion of the semiconductor active layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein said roughening the upper surface of the first portion of the semiconductor active layer comprises exposing the upper surface to a plasma etchant.

### Claim 4 (depends on 1)

The method of claim 1, wherein said selectively etching through the semiconductor active layer and the sacrificial layer comprises selectively etching the semiconductor active layer and the sacrificial layer in sequence to define a trench therein having a bottom that exposes the handling substrate; and wherein forming a multi-layer electrical interconnect network is preceded by filling the trench with an inorganic anchor.

### Claim 5 (depends on 4)

The method of claim 4, wherein selectively removing the sacrificial layer from between the first portion of the semiconductor active layer and the handling substrate comprises exposing a sidewall of the inorganic anchor.

### Claim 6 (depends on 4)

The method of claim 4, wherein the trench is a ring-shaped trench that surrounds the patterned substrate.

### Claim 7 (depends on 4)

The method of claim 4, wherein filling the trench with an inorganic anchor comprises depositing a semiconductor layer into the trench and onto the patterned substrate and then planarizing the deposited semiconductor layer to define a semiconductor anchor.

### Claim 8 (depends on 4)

The method of claim 4, wherein the multi-layer electrical interconnect network comprises a plurality of interlayer dielectric layers; and wherein said encapsulating is preceded by a step of selectively etching through the plurality of interlayer dielectric layers to expose the inorganic anchor.

### Claim 9 (depends on 8)

The method of claim 8, wherein said encapsulating comprises depositing the inorganic capping layer onto the exposed inorganic anchor.

### Claim 10 (depends on 8)

The method of claim 8, wherein the inorganic capping layer comprises amorphous silicon and the inorganic anchor comprises polysilicon.

### Claim 11 (depends on 3)

The method of claim 3, wherein said selectively etching through the semiconductor active layer and the sacrificial layer comprises selectively etching the semiconductor active layer and the sacrificial layer in sequence to define a trench therein having a bottom that exposes the handling substrate; and wherein forming a multi-layer electrical interconnect network is preceded by filling the trench with an inorganic anchor.

### Claim 12 (depends on 11)

The method of claim 11, wherein selectively removing the sacrificial layer from between the first portion of the semiconductor active layer and the handling substrate comprises exposing a sidewall of the inorganic anchor.

### Claim 13 (depends on 11)

The method of claim 11, wherein the trench is a rectangular ring-shaped trench that surrounds the patterned substrate.

### Claim 14 (depends on 11)

The method of claim 11, wherein filling the trench with an inorganic anchor comprises depositing a polysilicon layer into the trench and onto the patterned substrate and then removing excess portions of the deposited polysilicon layer using a planarization technique to define a semiconductor anchor.

### Claim 15 (depends on 11)

The method of claim 11, wherein the multi-layer electrical interconnect network comprises a plurality of interlayer dielectric layers; and wherein said encapsulating is preceded by a step of selectively etching through the plurality of interlayer dielectric layers to expose the inorganic anchor.

### Claim 16 (depends on 15)

The method of claim 15, wherein said encapsulating comprises depositing an amorphous silicon capping layer onto the exposed inorganic anchor.

### Claim 17 (depends on 1)

The method of claim 1, wherein said selectively etching through the semiconductor active layer and the sacrificial layer comprises selectively etching the semiconductor active layer and the sacrificial layer in sequence to define a trench therein having a bottom that exposes the handling substrate; and wherein forming a multi-layer electrical interconnect network is preceded by filling the trench with an inorganic anchor.

### Claim 18 (depends on 17)

The method of claim 17, wherein selectively removing the sacrificial layer from between the first portion of the semiconductor active layer and the handling substrate comprises exposing a sidewall of the inorganic anchor.