# US 9,040,424 B2 · Methods of forming single crystal silicon structures and semiconductor device structures including single crystal silicon structures

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- Number: US 9,040,424 B2
- Document ID: US9040424B2
- Status: Granted
- Kind: B2
- Application number: 13/416,834
- Filed: 2012-03-09
- Published: 2012-07-05
- Granted: 2015-05-26
- Earliest claimed: 2006-06-02
- Assignees: Micron Technology, Inc.
- Applicants: Janos Fucsko; David H. Wells; Patrick Flynn; Whonchee Lee
- Inventors: Janos Fucsko; David H. Wells; Patrick Flynn; Whonchee Lee
- Web page: https://patentgrep.com/patent/US9040424B2

## CPC

- H10P 50/644: {Anisotropic liquid etching (H10P50/61 takes precedence)}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10P 50/283: {by chemical means}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.

## Claims

### Claim 1

A method of forming at least one single crystal silicon structure, the method comprising:
forming at least one trench in a surface of a (100) silicon substrate;
forming a liner material over each of the surface of the (100) silicon substrate and portions of sidewalls of the at least one trench proximate the surface of the (100) silicon substrate; and
anisotropically wet etching exposed surfaces of the at least one trench to undercut the (100) silicon substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein anisotropically wet etching exposed surfaces of the at least one trench to undercut the (100) silicon substrate comprises treating the exposed surfaces with at least one wet etchant that etches the (100) silicon substrate slower along a (100) plane than along a (110) plane and a (111) plane.

### Claim 3 (depends on 2)

The method of claim 2, wherein the treating the exposed surfaces with at least one wet etchant that etches the (100) silicon substrate slower along a (100) plane than along a (110) plane and a (111) plane comprises treating the exposed surfaces with at least one wet etchant that etches the (100) silicon substrate along at least one of the (110) plane and the (111) plane at a rate of greater than about 150 Å/minute.

### Claim 4 (depends on 1)

The method of claim 1, wherein anisotropically wet etching exposed surfaces of the at least one trench to undercut the (100) silicon substrate comprises treating the exposed surfaces with a solution comprising at least one of a hydroxide and a fluoride.

### Claim 5 (depends on 4)

The method of claim 4, wherein an ionic strength of the solution is within a range of from about 5 to about 20.

### Claim 6 (depends on 4)

The method of claim 4, wherein a pH of the solution is within a range of from about 5.0 to about 9.0.

### Claim 7 (depends on 1)

The method of claim 1, wherein anisotropically wet etching exposed surfaces of the at least one trench to undercut the (100) silicon substrate comprises treating the exposed surfaces with a buffered fluoride etch solution comprising a fluoride component, an oxidizing agent, and an inorganic acid.

### Claim 8 (depends on 7)

The method of claim 7, wherein the buffered fluoride etch solution comprises approximately 10 percent by weight to approximately 35 percent by weight NH4F, approximately 3 percent by weight to approximately 20 percent by weight H2O2, and approximately 0.1 percent by weight to approximately 2 percent by weight inorganic acid.

### Claim 9 (depends on 1)

The method of claim 1, wherein anisotropically wet etching exposed surfaces of the at least one trench to undercut the (100) silicon substrate results in at least one etched surface having a surface roughness within a range of from about 1.25 Å RMS to about 1.30 Å RMS.

### Claim 10 (depends on 1)

The method of claim 1, wherein forming a liner material over the surface of the (100) silicon substrate and over portions of sidewalls of the at least one trench proximate the surface of the (100) silicon substrate comprises:
forming the liner material completely over each of the surface of the (100) silicon substrate and surfaces of the at least one trench; and
removing the liner material from each of a bottom surface of the at least one trench and other portions of the sidewalls of the at least one trench proximate the bottom surface.

### Claim 11 (depends on 1)

The method of claim 1, wherein anisotropically wet etching exposed surfaces of the at least one trench to undercut the (100) silicon substrate comprises anisotropically wet etching the exposed surfaces for a sufficient amount of time to form at least one (100) silicon pillar extending substantially vertically from the (100) silicon substrate to an integral (100) silicon structure having an outer perimeter extending laterally beyond an outer perimeter of the at least one (100) silicon pillar.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
performing a spin-on-dielectric fill of the at least one trench after anisotropically wet etching exposed surfaces of the at least one trench;
oxidizing the spin-on-dielectric fill; and
performing steam densification to remove the at least one (100) silicon pillar.

### Claim 13 (depends on 1)

The method of claim 1, further comprising removing the liner material after anisotropically wet etching the exposed surfaces of the at least one trench.

### Claim 14

A semiconductor device structure, comprising:
a (100) silicon substrate; and
a plurality of (100) silicon structures isolated from the (100) silicon substrate by a spin-on-dielectric material, each of the plurality of (100) silicon structures having an upper surface extending in a <100> direction and sidewalls extending in a <110> direction.

### Claim 15 (depends on 14)

The semiconductor device structure of claim 14, wherein at least one (100) silicon structure of the plurality of (100) silicon structures exhibits bottom surfaces angled relative to a vertical axis of the at least one (100) silicon structure.

### Claim 16 (depends on 15)

The semiconductor device structure of claim 15, wherein each of the bottom surfaces of the at least one (100) silicon structure of the plurality of (100) silicon structures exhibits an angle of 45 degrees relative to the vertical axis of the at least one (100) silicon structure.

### Claim 17 (depends on 14)

The semiconductor device structure of claim 14, wherein each of the plurality of (100) silicon structures is on the spin-on-dielectric material.

### Claim 18 (depends on 14)

The semiconductor device structure of claim 14, wherein the spin-on-dielectric material comprises an oxide material.

### Claim 19 (depends on 14)

The semiconductor device structure of claim 14, further comprising silicon nitride on the upper surface and the sidewalls of each of the plurality of (100) silicon structures.