# US 9,040,419 B2 · Semiconductor package and method for manufacturing the same

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- Number: US 9,040,419 B2
- Document ID: US9040419B2
- Status: Granted
- Kind: B2
- Application number: 14/334,406
- Filed: 2014-07-17
- Published: 2014-11-06
- Granted: 2015-05-26
- Earliest claimed: 2011-10-21
- Assignees: SK hynix Inc.
- Applicants: SK Hynix Inc.
- Inventors: Ho Young Son
- Web page: https://patentgrep.com/patent/US9040419B2

## CPC

- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/217: {comprising ring-shaped isolation structures outside of the via holes}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/46: comprising air gaps
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a semiconductor chip having a front surface and a back surface facing away from the front surface; a through electrode formed in the semiconductor chip and passing through the front surface and the back surface; and a contamination preventing layer formed in the semiconductor chip, the through electrode passing through the contamination preventing layer.

## Claims

### Claim 1

A method for manufacturing a semiconductor package, comprising:
preparing a semiconductor chip which has a front surface and a back surface facing away from the front surface;
forming a contamination preventing layer in the semiconductor chip;
forming a through electrode from the front surface of the semiconductor chip to a depth that passes through the contamination preventing layer; and
removing a portion of the back surface of the semiconductor chip to expose the through electrode.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the contamination preventing layer is formed by implanting impurities including argon (Ar).

### Claim 3 (depends on 1)

The method according to claim 1, wherein the through electrode is formed to have a depth deeper by 1˜10 μm than the contamination preventing layer when measured from the front surface of the semiconductor chip.

### Claim 4 (depends on 1)

The method according to claim 1, wherein, after the removing of the portion of the back surface of the semiconductor chip, the method further comprises:
forming an isolation pattern which surrounds each through electrode, by etching the back surface of the semiconductor chip to expose the contamination preventing layer.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the isolation pattern is formed to have a shape of a closed loop or a polygon when viewed from the top.

### Claim 6 (depends on 4)

The method according to claim 4, wherein, after the forming of the isolation pattern, the method further comprises:
forming a back side bump on an other end of the through electrode which is disposed on the back surface of the semiconductor chip.

### Claim 7 (depends on 1)

The method according to claim 1, wherein, after the removing of the portion of the back surface of the semiconductor chip, the method further comprises:
forming a dielectric layer on the back surface of the semiconductor chip; and
forming an isolation pattern which surrounds each through electrode, by etching the dielectric layer and the back surface of the semiconductor chip to expose the through electrode and the contamination preventing layer.

### Claim 8 (depends on 7)

The method according to claim 7, wherein the isolation pattern is formed to have the shape of a closed loop or a polygon when viewed from the top.

### Claim 9 (depends on 7)

The method according to claim 7, wherein, after the forming of the isolation pattern, the method further comprises:
forming a back side bump on an other end of the through electrode which is disposed on the back surface of the semiconductor chip.

### Claim 10 (depends on 1)

The method according to claim 1, wherein, after the forming of the through electrode, the method further comprises:
forming a front side bump on an one end of the through electrode which is disposed on the front surface of the semiconductor chip.