# US 9,040,418 B2 · Enhanced capture pads for through semiconductor vias > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,040,418 B2 - Document ID: US9040418B2 - Status: Granted - Kind: B2 - Application number: 14/076,233 - Filed: 2013-11-10 - Published: 2014-05-08 - Granted: 2015-05-26 - Earliest claimed: 2012-11-07 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Mukta G. Farooq; John A. Griesemer; Gary Lafontant; Kevin S. Petrarca; Richard P. Volant - Web page: https://patentgrep.com/patent/US9040418B2 ## CPC - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 90/00: Package configurations - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/01935: {by plating, e.g. electroless plating or electroplating} - H10W 72/01953: {by etching} - H10W 72/07254: {changes in dispositions} - H10W 72/07354: {changes in dispositions} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/347: {Dispositions of multiple die-attach connectors} - H10W 72/354: {comprising polymers} - H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/931: {Shapes of bond pads} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal; defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs. ## Claims ### Claim 1 A method of forming a capture pad on a semiconductor substrate comprising: providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled through silicon vias (TSVs) extending between the active side and the inactive side; filling the TSVs with a metal; defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; and filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion devoid of the insulator islands that follows an outline of each of the TSVs and a mixed portion comprising insulator islands dispersed in the metal. ### Claim 2 (depends on 1) The method of claim 1 wherein each of the capture pads have a first portion in direct contact with the TSVs and a second portion away from the TSVs and in direct contact with the first portion, the all metal portion being only in the second portion of each of the capture pads. ### Claim 3 (depends on 1) The method of claim 1 wherein each of the capture pads have a first portion in direct contact with the TSVs and a second portion away from the TSVs and in direct contact with the first portion, the all metal portion being in the first and second portions of each of the capture pads so as to extend entirely through each of the capture pads. ### Claim 4 (depends on 1) The method of claim 1 wherein the step of filling comprises filling the TSVs only partially with the metal so that the TSVs are recessed with respect to the at least one of the active side and the inactive side and wherein the step of filling the open areas includes filling the recessed TSVs. ### Claim 5 (depends on 1) The method of claim 1 wherein the step of filling comprises filling the TSVs fully with the metal, further comprising etching to recess the TSVs with respect to the at least one of the active side and the inactive side and wherein the step of filling the open areas includes filling the recessed TSVs. ### Claim 6 (depends on 1) The method of claim 1 further comprising forming at least one additional layer of material directly on the capture pads. ### Claim 7 (depends on 1) The method of claim 1 wherein the capture pad is on the active side of the semiconductor substrate. ### Claim 8 (depends on 1) The method of claim 1 wherein the capture pad is on the inactive side of the semiconductor substrate. ### Claim 9 (depends on 1) The method of claim 1 wherein the metal comprises copper. ### Claim 10 (depends on 1) The method of claim 1 further comprising joining the semiconductor substrate to at least one other semiconductor substrate to form a 3-dimensional semiconductor structure. ### Claim 11 A method of forming a capture pad on a semiconductor substrate comprising: providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled through silicon vias (TSVs) extending between the active side and the inactive side; filling the TSVs with a metal; defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; and filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having a TSV outline portion that follows an outline of each of the TSVs, at least part of each of the TSV outline portions being an all metal portion that follows the outline of each of the TSVs. ### Claim 12 (depends on 11) The method of claim 11 wherein the TSV outline portions have a first portion in direct contact with each of the TSVs and a second portion away from each of the TSVs and in direct contact with the first portion, the all metal portion being only in the second portion of each of the capture pads, the first and second portions being an entire thickness of each of the capture pads. ### Claim 13 (depends on 11) The method of claim 11 wherein the TSV outline portions have a first portion in direct contact with each of the TSVs and a second portion away from each of the TSVs and in direct contact with the first portion, the all metal portion being in the first and second portions of each of the capture pads so as to extend entirely through each of the capture pads. ### Claim 14 (depends on 11) The method of claim 11 wherein the step of filling comprises filling the TSVs only partially with the metal so that the TSVs are recessed with respect to the at least one of the active side and the inactive side and wherein the step of filling the open areas includes filling the recessed TSVs. ### Claim 15 (depends on 11) The method of claim 11 wherein the step of filling comprises filling the TSVs fully with the metal, further comprising etching to recess the TSVs with respect to the at least one of the active side and the inactive side and wherein the step of filling the open areas includes filling the recessed TSVs. ### Claim 16 (depends on 11) The method of claim 11 further comprising forming at least one additional layer of material directly on the capture pads. ### Claim 17 (depends on 11) The method of claim 11 wherein the capture pad is on the active side of the semiconductor substrate. ### Claim 18 (depends on 11) The method of claim 11 wherein the capture pad is on the inactive side of the semiconductor substrate. ### Claim 19 (depends on 11) The method of claim 11 wherein the metal comprises copper.