# US 9,040,417 B2 · Semiconductor devices and methods of manufacture thereof

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- Number: US 9,040,417 B2
- Document ID: US9040417B2
- Status: Granted
- Kind: B2
- Application number: 14/046,516
- Filed: 2013-10-04
- Published: 2015-04-09
- Granted: 2015-05-26
- Earliest claimed: 2013-10-04
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsin-Chieh Yao; Chung-Ju Lee; Tien-I Bao; Shau-Lin Shue
- Web page: https://patentgrep.com/patent/US9040417B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/085: {involving intermediate temporary filling with material}
- H10W 20/086: {involving buried masks}
- H10W 20/094: {by transforming insulators into conductors}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/4421: {the principal metal being copper}
- H10W 20/4424: {Copper alloys}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10W 20/0882: {wherein the dual damascene structure is in a photoresist layer}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an insulating material layer over a workpiece, patterning an upper portion of the insulating material layer with a conductive line pattern, and forming a stop layer comprising a metal oxide or a metal nitride over the patterned insulating material layer. A masking material is formed over the stop layer, and the masking material is patterned with a via pattern. The via pattern of the masking material is transferred to a lower portion of the insulating material layer.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming an insulating material layer over a workpiece;
patterning an upper portion of the insulating material layer with a conductive line pattern;
forming a stop layer comprising a metal oxide or a metal nitride over the patterned insulating material layer;
forming a masking material over the stop layer;
patterning the masking material with a via pattern; and
transferring the via pattern of the masking material to a lower portion of the insulating material layer.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising forming an etch stop layer comprising AlON over the workpiece, before forming the insulating material layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein forming the insulating material layer comprises forming a low dielectric constant (k) material having a dielectric constant of less than about 3.9.

### Claim 4 (depends on 1)

The method according to claim 1, wherein forming the insulating material layer comprises forming a layer comprising a thickness of about 30 nm to about 200 nm.

### Claim 5 (depends on 1)

The method according to claim 1, wherein forming the insulating material layer comprises forming SiOC.

### Claim 6 (depends on 1)

The method according to claim 1, wherein forming the stop layer comprises forming TiN or TiO.

### Claim 7 (depends on 1)

The method according to claim 1, wherein forming the stop layer comprises forming a layer comprising a thickness of about 1 nm to about 10 nm.

### Claim 8 (depends on 1)

The method according to claim 1, wherein transferring the via pattern of the masking material to the lower portion of the insulating material layer comprises etching the lower portion of the insulating material layer using the masking material as an etch mask.

### Claim 9

A method of manufacturing a semiconductor device, the method comprising:
forming an etch stop layer comprising AlON over a workpiece;
forming an insulating material layer over the etch stop layer;
patterning an upper portion of the insulating material layer with a conductive line pattern;
forming a masking material over the patterned insulating material layer;
patterning the masking material with a via pattern; and
transferring the via pattern of the masking material to a lower portion of the insulating material layer.

### Claim 10 (depends on 9)

The method according to claim 9, further comprising forming a stop layer comprising a TiN or TiO over the patterned insulating material layer, before forming the masking material.

### Claim 11 (depends on 9)

The method according to claim 9, further comprising:
removing a portion of the masking material; and
forming a conductive material over the patterned insulating material layer to form a conductive line in the conductive line pattern in the insulating material layer and a via in the via pattern in the insulating material layer.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the conductive line comprises a conductive line of an M(x+1) layer, wherein the workpiece includes a conductive line disposed in an Mx layer, and wherein the conductive line of the M(x+1) layer is substantially perpendicular to the conductive line in the Mx layer.

### Claim 13 (depends on 12)

The method according to claim 12, wherein the via is electrically coupled between the conductive line in the Mx layer and the conductive line of the M(x+1) layer.

### Claim 14 (depends on 13)

The method according to claim 13, wherein the conductive material grows through the etch stop layer comprising AlON to electrically couple the via to the conductive line in the Mx layer.

### Claim 15 (depends on 9)

The method according to claim 9, wherein forming the etch stop layer comprises forming a first etch stop layer, and wherein the method further comprises:
forming a second etch stop layer over the workpiece, before forming the insulating material layer, wherein transferring the via pattern of the masking material to the lower portion of the insulating material layer further comprises transferring the via pattern to the second etch stop layer; and
forming a first hard mask comprising a dielectric over the insulating material layer and forming a second hard mask comprising TiN over the first hard mask, before patterning the upper portion of the insulating material layer with the conductive line pattern, wherein patterning the upper portion of the insulating material layer with the conductive line pattern further comprises patterning the second hard mask and the first hard mask with the conductive line pattern, and wherein forming the masking material further comprises forming the masking material over the patterned second hard mask and the patterned first hard mask.

### Claim 16 (depends on 15)

The method according to claim 15, further comprising:
removing the masking material;
removing the second hard mask;
forming a conductive material over the patterned insulating material layer and the patterned first hard mask; and
removing the conductive material and the first hard mask from a top surface of the insulating material layer using a chemical-mechanical polishing (CMP) process or an etch process to form a conductive line in the conductive line pattern in the insulating material layer and a via in the via pattern in the insulating material layer and the etch stop layer.

### Claim 17

A method, comprising:
depositing over a substrate an insulating layer having a planar top surface and a planar bottom surface;
forming in the insulating layer a trench extending from the top surface of the insulating layer and having a trench bottom above the bottom surface of the insulating layer;
lining the trench with an etch stop layer;
filling the lined trench with a fill material;
etching the fill material and the etch stop layer to form a via pattern;
transferring the via pattern into the insulating layer to form a via extending from the trench bottom to the bottom surface of the insulating layer;
removing the etch stop layer; and
filling the trench and the via with a conductor.

### Claim 18 (depends on 17)

The method of claim 17, wherein the step of depositing over a substrate an insulating layer includes depositing a layer of SiOC.

### Claim 19 (depends on 17)

The method of claim 17, wherein the step of lining the trench with an etch stop layer includes depositing a layer selected from the group consisting of TiO, TiN, and combinations thereof.

### Claim 20 (depends on 17)

The method of claim 17, further comprising forming an underlying etch stop layer over the substrate prior to forming the insulating layer, the etch stop layer comprising AlON.