# US 9,040,416 B2 · Manufacturing method of metal wire and thin transistor array panel

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- Number: US 9,040,416 B2
- Document ID: US9040416B2
- Status: Granted
- Kind: B2
- Application number: 14/019,008
- Filed: 2013-09-05
- Published: 2014-11-13
- Granted: 2015-05-26
- Earliest claimed: 2013-05-10
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Dong-Jin Son
- Web page: https://patentgrep.com/patent/US9040416B2

## CPC

- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6737: {characterised by the electrode materials}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6743: {Silicon}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/123: Connection of the pixel electrodes to the thin film transistors [TFT]
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- H10K 71/60: Forming conductive regions or layers, e.g. electrodes
- H10K 59/12: Active-matrix OLED [AMOLED] displays
- H10K 59/1201: {Manufacture or treatment}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A manufacturing method of a wire including: forming a lower layer on a substrate; forming a middle layer on the lower layer; forming an upper layer on the middle layer; forming, exposing, and developing a photoresist layer on the upper layer to form a photoresist pattern; and etching the upper layer, the middle layer, and the lower layer by using the photoresist pattern as a mask to form a wire such that the upper layer covers an end of the middle layer.

## Claims

### Claim 1

A method of manufacturing a thin film transistor array panel, comprising:
forming a first lower layer on a substrate;
forming a first middle layer on the first lower layer;
forming a first upper layer on the first middle layer;
forming a photoresist pattern on the first upper layer using a first developing process;
forming a first signal line by etching the first upper layer, the first middle layer, and the first lower layer by using the photoresist pattern as a mask;
forming a thin film transistor connected to the first signal line;
forming a second signal line connected to the thin film transistor; and
forming a first electrode connected to the second signal line,
wherein:
the first upper layer covers an end of the first middle layer;
the first lower layer, the first middle layer, and the first upper layer are formed in a sputtering device including a mask aligned with edges of the substrate;
the mask is aligned to overlap the substrate by a first width when forming the first middle layer;
the mask is aligned to overlap the substrate by a second width when forming the first upper layer; and
the first width is less than the second width.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming of the second signal line further comprises:
forming a second lower layer on the substrate;
forming a second middle layer on the second lower layer;
forming a second upper layer on the second middle layer;
forming a second photoresist pattern on the second upper layer using a second developing process; and
etching the second upper layer, the second middle layer, and the second lower layer by using the photoresist pattern as a mask,
wherein the second upper layer covers the end of the second middle layer.

### Claim 3

A method of manufacturing a thin film transistor array panel, comprising:
forming a first lower layer on a substrate;
forming a first middle layer on the first lower layer;
forming a first upper layer on the first middle layer;
forming a photoresist pattern on the first upper layer using a first developing process;
forming a first signal line by etching the first upper layer, the first middle layer, and the first lower layer by using the photoresist pattern as a mask;
forming a thin film transistor connected to the first signal line;
forming a second signal line connected to the thin film transistor; and
forming a first electrode connected to the second signal line,
wherein:
the first upper layer covers an end of the first middle layer;
the forming of the second signal line further comprises:
forming a second lower layer on the substrate;
forming a second middle layer on the second lower layer;
forming a second upper layer on the second middle layer;
forming a second photoresist pattern on the second upper layer using a second developing process; and
etching the second upper layer, the second middle layer, and the second lower layer by using the photoresist pattern as a mask;
the second upper layer covers the end of the second middle layer;
the second lower layer, the second middle layer, and the second upper layer are formed in a sputtering device comprising a mask aligned with edges of the substrate;
the mask is aligned to overlap the substrate by a third width when forming the second middle layer;
the mask is aligned to overlap the substrate by a fourth width when forming the second upper layer; and
the third width is less than the fourth width.

### Claim 4 (depends on 3)

The method of claim 3, wherein:
the first middle layer and the second middle layer comprise Al or AlNiLa; and
the first lower layer, the second lower layer, the first upper layer, and the second upper layer comprise Mo.