# US 9,040,415 B2 · Semiconductor device and method of fabricating the same

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- Number: US 9,040,415 B2
- Document ID: US9040415B2
- Status: Granted
- Kind: B2
- Application number: 14/286,108
- Filed: 2014-05-23
- Published: 2015-02-19
- Granted: 2015-05-26
- Earliest claimed: 2013-08-16
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sang-Jine Park; Bo-Un Yoon; Young-Sang Youn; Jeong-Nam Han; Kee-Sang Kwon; Doo-Sung Yun; Byung-Kwon Cho; Ji-Hoon Cha
- Web page: https://patentgrep.com/patent/US9040415B2

## CPC

- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10P 50/283: {by chemical means}
- H10P 70/234: {the processing being the formation of vias or contact holes}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/096: {by contacting with gases, liquids or plasmas}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.

## Claims

### Claim 1

A method for forming a trench of a semiconductor device, the method comprising:
etching an oxide layer to form a trench therein;
conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench;
forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer; and
etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.

### Claim 2 (depends on 1)

The method of claim 1, wherein the conformally forming forms the first reaction layer including NH3.

### Claim 3 (depends on 1)

The method of claim 1, wherein the etching gas includes at least one of HF and HF3.

### Claim 4 (depends on 3)

The method of claim 3, wherein the etching the oxide layer on a lower portion of the second region comprises etching the oxide layer using the etching gas including at least one of an inert gas, N2 and NH3.

### Claim 5 (depends on 1)

The method of claim 1, wherein the forming a barrier layer comprises forming the barrier layer at a lower pressure than the etching the oxide layer on a lower portion of the second region.

### Claim 6 (depends on 1)

The method of claim 1, wherein the conformally forming forms the first reaction layer on a top surface of the oxide layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the forming a barrier layer forms the barrier layer on the top surface of the oxide layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein prior to the etching an oxide layer to form a trench therein, further comprising:
forming a gate structure on a substrate;
forming a source/drain on at least one side of the gate structure; and
forming the oxide layer covering the substrate and the gate structure,
wherein the trench is formed on the source/drain.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
forming a fin between the substrate and the gate structure.

### Claim 10 (depends on 8)

The method of claim 8, wherein
the etching an oxide layer to form a trench therein comprises exposing a top surface of the source/drain having a natural thin film formed thereon, and
the etching an oxide layer on a lower portion of the second region comprises exposing the top surface of the source/drain by removing the natural thin film.

### Claim 11 (depends on 10)

The method of claim 10, wherein the natural thin film is an oxide layer.

### Claim 12 (depends on 10)

The method of claim 10, after the etching an oxide layer on a lower portion of the second region, further comprising:
forming a contact in the trench.

### Claim 13

A method for fabricating a semiconductor device, the method comprising:
etching an insulation layer to form a trench therein, the insulation layer including a first region and a second region;
conformally forming a first reaction layer along a surface of the insulation layer;
forming a barrier layer by reacting an etching gas with the first reaction layer on a top surface of the first region, the first region being etched to a first thickness; and
etching the second region to a second thickness greater than the first thickness by reacting the etching gas with the first reaction layer on a top surface of the second region.

### Claim 14 (depends on 13)

The method of claim 13, wherein the etching an insulation layer etches an oxide layer.

### Claim 15 (depends on 13)

The method of claim 13, wherein
etching the second region includes using a first amount of the etching gas and a first pressure of the etching gas; and
forming a barrier layer includes using a second amount of the etching gas and a second pressure of the etching gas, the second amount and the second pressure less than the first amount and the first pressure.

### Claim 16

A method for forming a trench of a semiconductor device, the method comprising:
etching an insulation layer to form a trench therein, the insulation layer including a first region and a second region;
conformally forming a first reaction layer along a surface of the trench;
forming a barrier layer by reacting a first amount of etching gas at a first pressure with the first reaction layer on a top surface of the first region; and
etching the insulation layer by reacting a second amount of etching gas at a second pressure with the first reaction layer on a top surface of the second region, the second pressure being less than the first pressure and the second amount of etching gas being greater than the first amount of etching gas.

### Claim 17 (depends on 16)

The method of claim 16, wherein the etching an insulation layer etches an oxide layer.

### Claim 18 (depends on 16)

The method of claim 16, wherein the conformally forming forms the first reaction layer including NH3.

### Claim 19 (depends on 16)

The method of claim 16, wherein the etching gas includes at least one of HF and HF3.

### Claim 20 (depends on 16)

The method of claim 16, wherein prior to the etching an insulation layer to form a trench therein, further comprising:
forming a gate structure on a substrate;
forming a source/drain on at least one side of the gate structure; and
forming the insulation layer covering the substrate and the gate structure,
wherein the trench is formed on the source/drain.