# US 9,040,412 B2 · Three-dimensional vertically interconnected structure and fabricating method thereof

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- Number: US 9,040,412 B2
- Document ID: US9040412B2
- Status: Granted
- Kind: B2
- Application number: 14/449,155
- Filed: 2014-08-01
- Published: 2014-11-20
- Granted: 2015-05-26
- Earliest claimed: 2010-10-12
- Assignees: Peking University
- Applicants: Peking University
- Inventors: Shenglin Ma; Yunhui Zhu; Xin Sun; Yufeng Jin; Min Miao
- Web page: https://patentgrep.com/patent/US9040412B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/217: {comprising ring-shaped isolation structures outside of the via holes}
- H10W 20/42: Vias, e.g. via plugs
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07331: {Connecting techniques}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/271: {the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement}
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method therefor. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face. An adhesive material is used for adhesion between adjacent layers of the chips while each layer of the chips contains a substrate layer and a dielectric layer from bottom to top. A front surface of the chip has a first concave, which is filled with metal to form a first electrical conductive ring that connects to microelectronic devices inside the chip via a redistribution layer. A first through layers of chips hole with a first micro electrical conductive pole inside, penetrates the stacked chips. The structure in the present invention enhances the electric interconnection and the bonding between adjacent layers of chips while the instant fabricating method simplifies the process and increases the yield.

## Claims

### Claim 1

A fabricating method for a three-dimensional vertically interconnected structure, characterized by comprising steps of:
S1, conducting lithography on a surface of a single layer of silicon wafer or chip which has or has not undergone a thinning process to form photo-resist mask for annular patterns, then sequentially etching a first dielectric layer and a substrate layer of the single layer of wafer or chip to form a first concave of fergitun-shape;
S2, depositing a barrier layer and a seed layer to cover an inside wall of the first concave, and then copper electroplating to fill the first concave, for forming a first electrical conductive ring;
S3, forming a redistribution layer which connects the first electrical conductive ring with microelectronic devices inside the wafer or chip, wherein the redistribution layer comprises a second dielectric layer and a metallic interconnection layer;
S4, etching the second dielectric layer of the redistribution layer and the first dielectric layer of the wafer or chip sequentially to form a first through-silicon-via (TSV) inside the first electrical conductive ring, wherein the first TSV has the same radius and center as the inner ring of the first electrical conductive ring;
S5, sequentially stacking single layers of wafers or chips which have completed steps S1-S4 and aligning the same, and adjacent wafers or chips being adhered to each other by using organics or metallic solders;
S6, depositing a seed layer and electroplating copper on one side of the multi-stacked layers of wafers or chips to seal a first through layers of wafers or chips hole that is constituted of vertically aligned TSVs; filling the first through layers of wafers or chips holes which penetrate the multi-layered stacks from bottom to top with copper electroplating to form a first micro electrical conductive pole, and removing the electroplated copper and seed layer, for finishing the fabrication of the three-dimensional vertically interconnected structure.

### Claim 2 (depends on 1)

The fabricating method for the three-dimensional vertically interconnected structure of claim 1, characterized by, before depositing the barrier layer and the seed layer of step S2, depositing an insulation layer to cover the inside wall of the first concave, sillica or polyimide being selected as the insulation layer, and a method of sputtering or plasma enhanced chemical vapor deposition being used for depositing the insulation layer.

### Claim 3 (depends on 2)

The fabricating method for the three-dimensional vertically interconnected structure of claim 2, characterized by, after step S2, repeating steps S1-S2 to form a second electrical conductive ring and/or a thermal conductive ring having the same structure on a front surface of a layer of wafer or chip and/or a backside surface.

### Claim 4 (depends on 3)

The fabricating method for the three-dimensional vertically interconnected structure of claim 3, characterized by, in step S3, forming a grounding electrical conductive layer and/or a thermal conductive layer on a front surface of the layer of wafer or chip and/or a backside surface; the grounding electrical conductive layer is connected with the second electrical conductive ring, and the thermal conductive layer is connected with the thermal conductive ring.

### Claim 5 (depends on 1)

The fabricating method for the three-dimensional vertically interconnected structure of claim 1, characterized by, in step S5, patterning the adhesive material to form micro-fluid channels for heat dissipation.

### Claim 6

A fabricating method for a three-dimensional vertically interconnected structure, characterized by comprising steps of:
S1, conducting lithography on a front surface of a single layer of silicon wafer or chip to form a photo-resist mask for annular patterns, then sequentially etching a dielectric layer and a substrate layer of the single layer of wafer or chip to form a first concave of fergitun-shape;
S2, depositing a barrier layer and a seed layer to cover the inside wall of the first concave, and electroplating copper to fill the first concave, for forming a first electrical conductive ring;
S3, forming a redistribution layer which connects the first electrical conductive ring with microelectronic devices inside the wafer or chip, wherein the redistribution layer comprises a dielectric layer and a metallic interconnection layer;
S4, sequentially etching the dielectric layer of the redistribution layer and the dielectric layer of the wafer or chip to form a blind TSV inside the first electrical conductive ring, the blind TSV having the same radius and center as the inner ring of the first conductive ring;
S5, stacking two layers of wafers or chips which have completed steps S1-S4 face-to-face and aligning the same, wherein the wafers or chips being adhered to each other by using organics or metallic solders;
S6, conducting a thinning process on both sides of the layers of wafers or chips which are stacked until the blind TSVs of each layer of wafer or chip is exposed to implement a through layers of wafers or chips hole;
S7, stacking a single layer of wafer or chip which has completed steps S1-S4 on the wafers or chips which have completed steps S1-S6, and adhering the same, and then repeating step S6 to implement a stacking of three or more layers of wafers or chips;
S8, depositing a seed layer and conducting copper electroplating on one side of the stacked wafers or chips to seal the through layers of wafers or chips hole; filling the through layers of wafers or chips holes which penetrate the stacked wafers or chips from bottom to top with copper electroplating to form a micro electrical conductive pole, and removing the electroplated copper and the seed layer, for finishing the fabrication of the three-dimensional vertically interconnected structure.

### Claim 7 (depends on 6)

The fabricating method for the three-dimensional vertically interconnected structure of claim 6, characterized by, in step S3, forming a second conductive ring and/or a thermal conductive ring on an active region surface of the single layer of wafer or chip and/or a backside surface.

### Claim 8 (depends on 7)

The fabricating method for the three-dimensional vertically interconnected structure of claim 7, characterized by, in step S3, forming a grounding electrical conductive layer and/or a thermal conductive layer on a front surface and/or a backside surface of a layer of wafer or chip; the grounding electrical conductive layer is connected with the second electrical conductive ring, and the thermal conductive layer is connected with the thermal conductive ring.

### Claim 9 (depends on 6)

The fabricating method for the three-dimensional vertically interconnected structure of claim 6, characterized by, in step S5, patterning the adhesive material to form micro-fluid channels for heat dissipation.

### Claim 10 (depends on 6, 7, 8, 9)

The fabricating method for the three-dimensional vertically interconnected structure of any one of claims 6-9, characterized by, after step S4, depositing an insulation layer to cover the inside wall of the blind TSV, and conducting etching at an opening of the blind hole, to remove the insulation layer inside the conductive ring and expose the sidewall of the first electrical conductive ring.